US 5,859,986 A · Bandwidth efficient method and means for resynchronizing a master and slave over a clocked, arbitrated, bidirectional multistate parallel bus using local data recirculation, wait states, and cycle stealing

Abstract

A method and means for efficiently utilizing bus bandwidth among processors and input/output devices burst coupled in master/slave pairs over a clocked, arbitrated, bidirectional, multistate, local communications bus. The method resynchronizes arbitrated masters and selected slaves perturbed during their bus-coupled transactions by recirculating data during a write operation at a bus master in the absence of a slave acceptance signal, or recirculating by a slave in the absence of a master response. The recirculating master or slave responsive to a delayed indication from its passive opposite then sends out the data over the bus at an integral multiple of the clock rate.

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Claims16

Dependent claims

A method and means for efficiently utilizing bus bandwidth among processors and input/output devices burst coupled in at least master/slave pairs over a clocked, arbitrated, bidirectional, multistate, local communications bus, comprising the steps of:

(a) arbitrating among all bus-attached processors and I/O units and selecting the processor or I/O unit presenting the highest priority;
(b) causing the arbitrated master to access at least one slave by address and byte count notification over the bus;
and
(c) resynchronizing an arbitrated master and at least one selected slave perturbed during their bus-coupled transactions by
(1) causing the arbitrated master to assume a wait state and locally recirculate data during a write operation in the absence of a slave acceptance signal or mutually exclusively causing the selected slave to locally recirculate data in the absence of a master response;
and
(2) causing the recirculating master or slave to send the data over the bus at an integral multiple of the clock rate responsive to a delayed indication from its respective paired slave or master.

4 more elements

A method for transferring data from at least one processor or input/output (I/O) unit to at least one other processor or I/O unit over a clocked, arbitrated, bidirectional, multistate (tristate) parallel bus, said bus including data, control, and timing signal paths, each processor or I/O unit being adapted to assume a master or slave data transmission role, arbitration determining a master among the processors and I/O units by priority at any given period of time, comprising the steps of:

(a) arbitrating among all bus-attached processors and I/O units and selecting the processor or I/O unit presenting the highest priority;
(b) during a first clock cycle, accessing at least one slave by address and byte count notification over the data and control paths combined as sent from the arbitrated master;
(c) during a second clock cycle, designating the direction of data transfer by the arbitrated master to the addressed slave and transmitting a data timing indication and at least some of the data if the transfer direction is master toward slave;
(d) in the event that the slave requires more than one clock cycle to decode the address and process the function designated by step (c), delaying any acceptance by the slave to the master;
(e) in the event that the transfer direction was from the master toward the slave, recirculating any data locally (off bus) by the master starting at a predetermined intermediate point until either an acceptance signal is received from the slave or a time out occurs;
and
(f) upon receipt of an acceptance from the slave, causing the master to send the remaining data to the slave.

4 more elements

A method for transferring data from at least one processor or input/output (I/O) unit to at least one other processor or I/O unit over a clocked, arbitrated, bidirectional, multistate (tristate) parallel bus, said bus including data, control, and timing signal paths, each processor or I/O unit being adapted to assume a master or slave data transmission role and to be at least partially ordered on the basis of an assigned priority, arbitration determining a master among the processors and I/O units by priority at any given period of time, any arbitrated master initiating data transfers to one or more slaves designated by address and data string length (byte count), interactions between masters and slaves being of the demand/response (acceptance signal) type, said bus always being susceptible to seizure by a master of higher priority, comprising the steps of:

(a) arbitrating among all bus-attached processors and I/O units and selecting the processor or I/O unit presenting the highest priority;
(b) during a first clock cycle, accessing at least one slave by address and byte count notification over the data and control paths combined from the arbitrated master;
(c) during a second clock cycle, designating the direction of data transfer by the arbitrated master to the addressed slave and transmitting at least some of the data if the transfer direction is master toward slave;
(d) in the event that the slave requires more than one clock cycle to decode the address and process the function designated by step (c), delaying any acceptance by the slave to the master;
(e) in the event that the transfer direction was from the master toward the slave and the arbitrated master does not receive acceptance signals from the slave, recirculating any data locally (off bus) by the master, starting at a predetermined intermediate point in time, until either an acceptance signal is received from the slave or a time out occurs;
and
(f) upon receipt of an acceptance signal from the slave, sending the remaining data by the master at a predetermined integral number of clock cycles.

4 more elements

In a data transmission system comprising a plurality of processors and input/output units coupled over a clocked, arbitrated, bidirectional, multistate bus, said bus including data, control, and timing signal paths, each processor or I/O unit being adapted to assume a master or slave data transmission role, arbitration determining a master among the processors and I/O units by priority at any given period of time, wherein the improvement comprises in combination:

(a) means for arbitrating among all bus-attached processors and I/O units and for selecting the processor or I/O unit presenting the highest priority;
(b) an arbitrated master including
(1) means responsive during a first clock cycle for accessing at least one slave by address and byte count notification over the data and control paths combined;
(2) means responsive during a second clock cycle for designating the direction of data transfer between the arbitrated master and the addressed slave and for transmitting at least some of the data if the transfer direction is that of the master toward the addressed slave;
and
(3) means responsive to any absence of an acceptance by the slave for recirculating the data locally (off bus) and for transmitting the remaining data to the slave over the bus at a predetermined integral number of clock cycles;
and
(c) means for seizing the bus at any time by another master presenting a priority higher than the arbitrated master, said means including means for cycle stealing from the arbitrated master by said higher priority master, and for causing said arbitrated master to assume a wait state until the higher priority master relinquishes the bus.

5 more elements

Dependencies are inferred from the claim text.

Description5,358 words

Summary1,703 words

#This invention relates to a method and means for efficiently utilizing bus bandwidth among processors and input/output devices burst coupled in master/slave pairs over a clocked, arbitrated, bidirectional, multistate, local communications bus. More particularly, the invention relates to resynchronizing arbitrated masters and selected slaves perturbed during their bus-coupled transactions without resorting to large local buffers or complex task-switched states or the like.

#Aspects of a Local Communications Bus

#A bus is a parallel operation expressed as a bidirectional set of lines to which an unlimited number of stations (masters/slaves) are coupled. In contrast, a loop is a transmission path closed upon itself. Even though a bus is not closed, nevertheless it is a time-shared path so that distances, as measured in propagation time (delay) along the path, will determine the minimum cycle time.

Brief description of the drawings7 figures

#FIG. 1 shows a block diagram of a prior art parallel bus attaching diverse processors, subsystems, and devices.

#FIG. 2A depicts a contemporary clocked, arbitrated, multistate bus emphasizing distributed arbitration and various control, clocking, data, and other lines coupling each processor and unit.

#FIG. 2B illustrates a chip interface diagram having a JTAG register scanning interface well known in the prior art.

Detailed description3,506 words

#Bus-coupled Systems in General

#Referring now to FIG. 1, there is shown a block diagram of a prior art parallel bus 9 attaching diverse processors 1 and 5, a subsystem 3, and an input/output device 7 over counterpart couplings 11, 13, 15, and 17. The bus 9 is an open parallel transmission path whose basic cycle time is determined by the driving and receiving registers, their associated drivers and receivers, the bus length, and the number of attached devices. The bus-based system further includes logic internal to each of the attached units and arbitration (not shown). Significantly, any of the processors 1 or 5, the subsystem 3, or device may request access to the bus 9 and ultimately to any of the other attached units as a destination. They are assigned a predetermined priority and the arbitration unit will determine which among the units presenting priority will be given access to the bus. The bus is preferably bidirectional, although such is not a requirement. Bidirectionality simplifies processing since any of the units may become an arbitrated master and one or more of the other units may become a selected slave, and the direction of data transfer varies as a function of whether the master requests a read or a write operation.

#Bus-coupled System with Arbitration, Data Address, Controls, and Timing/Clock Signals

Bandwidth efficient method and means for resynchronizing a master and slave over a clocked, arbitrated, bidirectional multistate parallel bus using local data recirculation, wait states, and cycle stealing

Life of this patent

Bandwidth efficient method and means for resynchronizing a master and slave over a clocked, arbitrated, bidirectional multistate parallel bus using local data recirculation, wait states, and cycle stealing

Life of this patent

Life of this patent

Abstract

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Claims16

Description5,358 words

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Classification2 codes

Life of this patent

Description5,358 words