US 5,859,975 AGranted

Parallel processing computer system having shared coherent memory and interconnections utilizing separate undirectional request and response lines for direct communication or using crossbar switching device

AssigneeHewlett-Packard Company

InventorsTony Mahlon Brewer, Thomas Lee Watson, David Michael Chastain

Life of this patent

Estimating the term…

Loading patent…

Abstract

There is disclosed a shared multiprocessing system with several nodes, or processing units, interconnected together for communication purposes by a dual channeled crossbar switch. Several such multichannel crossbar switches can be linked together to form a large cohesive processing system where processing units from one node can access memory from another node on the same crossbar or from another node on a different crossbar. The interconnection between crossbars is accomplished by a circular ring. In operation, the system allows for long memory latencies while not increasing the length of short (local) memory latencies. This is, accomplished by storing the bulk of long latency requests at the local processing unit and only sending the request when there is an actual availability of communication capacity to handle the long latency request.

Claims14

Dependent claims

A multiprocessor system having a plurality of nodes, each node having local processing and shared, coherent memory capabilities organized into units, said system operable such that the processor or the memory from any unit can access the processor or the memory from any other unit, said system comprising:

a first switch for interconnecting a plurality of said memory and processors from a plurality of said units, said switch having first and second subswitches, each said subswitch operable independent of each other, said switch and subswitches replicated along crossbar ports with each port associated with a particular memory and processor unit, said switch including
dual unidirectional communication connections between said memory capability via a coherent memory controller of said associated unit and said associated port, one direction of said dual unidirectional communication being with said first subswitch of said associated port and the other direction of said dual unidirectional communication being with said second subswitch of said associated port and including
unidirectional communication connections between said processor capability of said associated unit and said associated port, one direction of said dual unidirectional communication being with said first subswitch of said associated port and the other direction of said dual unidirectional communication being with said second subswitch of said associated port;
and
means, using said dual unidirectional connections, for effecting bidirectional communication capability between said memory via said coherent controller and said processing capabilities, wherein the one direction is for communicating, certain requests and the other direction is for communicating certain responses.

2 more elements

The method of communicating between a shared coherent memory and a processor in a computer system, said method comprising the steps of:

communicating certain requests from said memory to said processor over a first unidirectional communication link via a coherent memory controller;
communicating certain responses from said processor to said memory over a second unidirectional communication link via said coherent memory controller;
communicating certain requests from said processor to a switching device over a third unidirectional communication link;
communicating certain requests from said switching device to said memory via said coherent memory controller over a fourth unidirectional communication link;
communicating certain responses from said memory via said coherent memory controller to said switching device over a fifth unidirectional communication link;
and
communicating certain responses from said switching device to said processor over a sixth communication link.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/695,266Filed 9 Aug 1996 · continuation
Priority: 15 Dec 1993
Granted: 12 Jan 1999
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 15/17375
Non hierarchical topologies: one dimensional, e.g. linear array, ring
G06F 13/1657
In a multiprocessor architecture: access to multiple memories
G06F 13/1663
In a multiprocessor architecture: access to shared memory
G06F 13/4022
Coupling between buses: using switching circuits, e.g. switching matrix, connection or expansion network