Renumbered array architecture for multi-array memories
AssigneeTownsend and Townsend and Crew LLP
InventorRobert J. Proebsting
Life of this patent
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Abstract
A method and apparatus for renumbering memory arrays may be used in memory systems having a target memory capacity formed from a number (N) of memory arrays. Upon powerup of the memory system, if a portion (M) of the N memory arrays are identified as defective, the memory arrays are renumbered from 0 to (N-M) to provide a logically continuous memory system having a smaller memory capacity than the target memory capacity.
Claims9
A method for renumbering memory arrays in a memory system having a target memory capacity, and having a number (N) of memory arrays, the method comprising the steps of:
- identifying a portion (M) of said (N) memory arrays which are defective;
- renumbering said memory arrays from 0 to (N-M) to provide a logically continuous memory system having a revised memory capacity smaller than said target memory capacity.
A method for numbering memory arrays in a memory system, the method comprising the steps of:
- providing a number (N) of memory arrays, each of said memory arrays coupled to an address latch;
- disabling a portion (M) of the (N) memory arrays which are defective;
- bypassing a number (M) of shift registers, each of said bypassed shift registers associated with one of said (M) defective memory arrays;
- and
- storing an array address in each of said address latches so that each non-defective memory array is identified by a unique array address.
A memory device having a target memory capacity, the device comprising:
- a number (N) of memory arrays, each of said memory arrays coupled to an array address latch;
- means for disabling a number (M) of said memory arrays when said number M of memory arrays are defective;
- address generation means, coupled to said array address latches, for generating a number (N-M) of sequential array addresses stored in said array address latches.
A video memory system operable with a target memory capacity having N memory arrays, and with a reduced memory capacity having less than N memory arrays, the system comprising:
- a number N of array structures, each including a memory array having an address stored in an address latch, said memory array addressed by address lines presented to an array decoder;
- address generation means, coupled to each of said address latches of said N array structures, for sequentially generating an address for each of said N array structures during a powerup cycle of said video memory system.
Dependencies are inferred from the claim text.