Dual modulus prescaler
AssigneeMotorola, Inc.
InventorsCarl L. Shurboff, Matsuo M. Marti
Life of this patent
Estimating the term…
Abstract
A dual-modulus prescaler (100) has improved performance for high-speed operation. A timing signal is developed from a flip flop circuit (106) two and one-half clock cycles before the last stage of the prescaler is clocked. The timing signal is used to produce a selector signal to gate a multiplexer (112). Because of the early generation of the timing signal, the multiplexer selection process is removed from the critical path. The remaining delay through the multiplexer is minimal to minimize the critical path of the prescaler.
Claims13
A prescaler comprising:
- a plurality of sequentially coupled flip flop circuits having an input;
- a switch circuit coupled to the input, the switch circuit receiving an output signal from a last flip flop circuit and providing a feedback signal to the input in response to a selector signal;
- and
- a logic circuit coupled to the switch circuit for providing the selector signal in response to a timing signal from a flip flop circuit, the logic circuit providing the selector signal before the last flip flop circuit provides the output signal.
A prescaler for dividing a clock signal by a predetermined modulus and producing an output signal, the prescaler comprising:
- a plurality of flip flop circuits, each flip flop circuit having a clock input for receiving the clock signal, the plurality of flip flop circuits being sequentially coupled for clocking data through the plurality of flip flop circuits in response to the clock signal;
- a multiplexer responsive to a selector signal for selectively coupling one of an output of a last flip flop circuit of the plurality of flip flop circuits and an output of a next-to-last flip flop circuit to a multiplexer output, the multiplexer output being coupled to an input of a first flip flop circuit;
- and
- a logic circuit coupled to one flip flop circuit of the plurality of flip flop circuits for receiving a timing signal and providing the selector signal in response to the timing signal to remove the selector signal from a critical path of the prescaler.
A dual modulus prescaler comprising:
- a clock input for receiving a clock signal having a predetermined frequency;
- a plurality of sequentially coupled flip flop circuits, each flip flop circuit having a clock input for receiving the clock signal, each flip circuit including a master latch and a slave latch, the slave latch driven by the master latch, a first flip flop circuit having an input for receiving a feedback signal, a last flip flop circuit having an output for providing a first output signal, a next-to-last flip flop circuit having an output for providing a second output signal;
- a switch circuit coupling the output to the input, the switch circuit providing a feedback signal to the input in response to one of the first output signal and the second output signal in response to a selector signal;
- and
- a logic circuit coupled to a flip flop circuit for detecting a timing signal and providing the selector signal to the switch circuit for selecting one of the first output signal and the second output signal, the first output signal corresponding to a first modulus and the second output signal corresponding to a second modulus.
Dependencies are inferred from the claim text.