High speed viterbi decoder

A Viterbi decorder comprising:

• a branch metric arithmetic unit for computing the branch metrics of signals inputted from an input terminal;
• a normalization arithmetic unit for providing normalized state values by utilizing maximum likelihood state values and branch metric values output from said branch metric arithmetic unit;
• an ACS arithmetic unit for computing state values and survivor path information by receiving a state value computed at a preceding time point and by receiving an output of said normalization arithmetic unit;
• a state value storing device for storing and outputting to said ACS arithmetic unit said state value computed at the preceding time point, and for storing state values output from said ACS arithmetic unit;
• a maximum likelihood state value detecting device for detecting a maximum likelihood state value of a preceding time from a normalized output of said state value storing device;
• a maximum likelihood state value storing device for storing the maximum likelihood state value output from said maximum likelihood state value detecting device so as to output the maximum likelihood state value to said normalization arithmetic unit;
• a traceback control device for outputting decoded data after carrying out a decoding by receiving an address of a state having the maximum likelihood state value of said maximum likelihood state detecting device so as to output decoded data;
• and
• a path storing device for storing a survivor path information output from said ACS arithmetic unit.

A high speed Viterbi decoding method based on a normalization, comprising the steps of:

• making a judgment as to whether the maximum value of survivor state values of a state value storing device exceeds a predetermined threshold value;
• deciding an existence or absence of a normalization demand;
• and
• dividing by 2 for all the survivor state values so as to execute a normalization operation.

A high speed Viterbi decoder based on a normalization operation comprising:

• a branch metric arithmetic unit for computing the branch metrics of signals inputted from an input terminal;
• an ACS arithmetic unit for receiving state values computed at a preceding time point and branch metric values from said branch metric arithmetic unit so as to compute state values and a survivor path information;
• a multiplexer device consisting of multiplexers as many as the number states, and for receiving the output of said ACS arithmetic unit so as to either output it without processing in accordance with a normalization arithmetic demand, or so as to output a "divided by 2" normalized result;
• a state value storing device for storing the state values of said multiplexer device so as to output them to said ACS arithmetic unit;
• a normalization demanding device for detecting as to whether the maximum value of the state values of said state value storing device exceeds a predetermined threshold value, so as to output the result to said multiplexer device;
• and
• a traceback device consisting of:
• a path storing device for storing the survivor path information of said ACS arithmetic unit;
• and a traceback control device for controlling a traceback, so as to output a decoded data based on the traceback.

A high-speed Viterbi decoder comprising:

• a branch metric arithmetic means for computing branch metrics of signals inputted from an input terminal;
• an ACS arithmetic means for receiving state values computed at a preceding time and branch metric values from said branch metric arithmetic means so as to compute state values and survivor path information;
• a normalization arithmetic means for normalizing the state values by utilizing maximum likelihood state values and the state values computed by said ACS arithmetic means;
• a state value storing means for storing a state value of said normalization arithmetic means;
• a maximum likelihood state value detecting means for detecting a maximum likelihood state value from said state value storing means;
• a maximum likelihood state value storing means for storing a maximum likelihood state value output from said maximum likelihood state value detecting means so as to supply it to said normalization arithmetic means;
• a path storing means for storing a survivor path information of said ACS arithmetic means;
• and
• a trace back control means for controlling the path storing means utilizing an address having the maximum likelihood state value from said maximum likelihood state value detecting means so as to output decoded data.

A high-speed Viterbi decoder comprising:

• a branch metric arithmetic means for computing branch metrics of signals inputted from an input terminal;
• a normalization arithmetic means for normalizing the branch metrics by utilizing a maximum likelihood state value;
• an ACS arithmetic means for using state values computed at a preceding time and output values of said normalization arithmetic means so as to computer a new state value and survivor path information;
• a state value storing means for storing a state value of said ACS arithmetic means so as to output it to said ACS arithmetic means;
• a maximum likelihood state value detecting means for detect a maximum likelihood state value from an output of said state value storing means;
• a maximum likelihood state value storing means for storing a maximum likelihood state value output from said maximum likelihood state value detecting means so as to supply it to said normalization arithmetic means;
• a path storing means for storing survivor path information of said ACS arithmetic means;
• and
• a trace back control means for controlling the path storing means by utilizing an address having the maximum likelihood state value from said maximum likelihood state value detecting means so as to output decoded data.