Parallel cyclic redundancy code error detection

Abstract

An error detection circuit and method for detecting errors in data using a cyclic redundancy code which includes a plurality of first EXCLUSIVE OR gates each of which receives one bit of input data and one bit of a first portion of remainder data. Each first EXCLUSIVE OR gate outputs the EXCLUSIVE OR of the input data bits and the first remainder data bits to a corresponding one of a plurality of first registers to provide input data to the registers such that the registers store the result of the EXCLUSIVE OR operation. Each of a plurality of second EXCLUSIVE OR gates receives the output of a corresponding one of the plurality of first registers and receives one bit of a second portion of remainder data. Each second EXCLUSIVE OR outputs the EXCLUSIVE OR of these two inputs to a corresponding one of a plurality of second registers which store this second result. Each of the second registers has an output for outputing their stored value.

Dependencies are inferred from the claim text.