Modular switch element for shared memory switch fabric

A modular switch element for shared memory switch fabric, comprising:

• a plurality of input ports;
• a plurality of output ports;
• a memory array coupled to the plurality of input ports and to the plurality of output ports;
• and
• a control logic unit coupled to the plurality of input ports, to the plurality of output ports, and to the memory array, the control logic receiving a size signal representative of a number of modular switch elements in a shared memory switch fabric, the control logic unit writing data input to the plurality of input ports into the memory array responsive to a first set of control signals and the size signal, and the control logic reading data stored in the memory array to the plurality of output ports responsive to a second set of control signals and the size signal;
• and
• a plurality of input shift-registers and a plurality of output shift-registers coupled to the plurality of input ports and to the plurality of output ports, respectively.

A modular switch element for shared memory switch fabric, comprising:

• N M-bit input shift-registers, where N and M are a non-zero integers;
• N input registers coupled to the N M-bit input shift-registers;
• a memory array coupled to the N input registers;
• N output registers coupled to the memory array;
• N M-bit output shift-registers coupled to the N output registers;
• N input address registers;
• N output address registers;
• and
• control logic coupled to the N M-bit input shift-registers, to the N input registers, to the memory array, to the N output registers, to the N M-bit output shift-registers, to the N input address registers, and to the N output address registers,
• wherein each the N M-bit input shift-registers serially receives a data cell and outputs an M-bit datum to one of the N input registers, where the control logic writes each M-bit datum to a differing location in the memory array, the location determined responsive to a differing one to the N input address registers and to a start frame signal, where the control logic reads a differing location in the memory array to a differing one of the N output registers responsive to the N output address registers, and where the N M-bit output shift-registers receive in parallel N M-bit data cells from the N output registers and serially output the N M-bit data cells.

A shared memory switch fabric for routing data cells between I inputs and O outputs, each data cell comprising B bits, where I, O, and B are non-zero integers, the shared memory switch fabric comprising:

• E modular switch elements, where E is a non-zero integer, wherein a Jth one of the E modular switch elements further comprises, where J is an integer index ranging from 0 to (E-1):
• I input ports coupled to receive the Jth bit of each of the I inputs;
• a memory array coupled to the I input ports;
• O output ports coupled to the memory array to output the Jth bit of each of the O outputs;
• control logic coupled to the I input ports, to the memory array and to the O output ports, the control logic writing data input to the I input ports into the memory array responsive to a first set of control signals and the control logic reading data stored in the memory array to the O output ports responsive to a second set of control signals;
• and
• a controller coupled to each of the E modular switch elements, the controller generating the first and second set of control signals.