US 5,859,810 A · Pulse generation circuit and method for synchronized data loading in an output pre-buffer

Abstract

A memory device that includes an internal bus for the transfer of data and reporting signals from and to the memory and output pre-buffers for the transfer of data to output terminals of said memory, a pulse generation circuit for the synchronized loading of data in an output pre-buffer. Additional circuitry is provided that includes a synchronization circuit; a transmission path delay reproduction circuit for reproducing the propagation delays of the data transmitted to the output terminals; and a pre-buffer delay reproduction circuit for reproducing the propagation delays of the output pre-buffers. The synchronization circuit is adapted to synchronize the generation of at least one pulse that is synchronized with the propagation delays reproduced by the transmission path delay reproduction circuit, and the pulse is adapted to enable the loading of the data in the output pre-buffers. The synchronization of the pulse is provided as a consequence of the assured presence of the data, and the synchronous pulse is restored after a time that is equal to the delay introduced by the pre-buffer delay reproduction circuit for reproducing the propagation delays of the output pre-buffers, so as to update the configuration of the output pre-buffers in the time interval determined by the synchronous pulse.

Claims38

Dependent claims

A memory device including a memory matrix;

an internal bus for the transfer of data and reporting signals from and to the memory matrix;
output pre-buffers for the transfer of data to output terminals of the memory matrix;
and
a pulse generation circuit for the synchronized loading of data in an output pre-buffer, further comprising:
synchronization generation means;
means for reproducing the propagation delays of the data transmitted to said output terminals;
and
means for reproducing the propagation delays of said output pre-buffers;
said synchronization means being adapted to synchronize the generation of at least one pulse that is synchronized with the propagation delays reproduced by said data propagation delay reproduction means, said pulse enabling the loading of the data in said output pre-buffers, said synchronization being provided as a consequence of the assured presence of the data, said synchronous pulse being restored after a time that is equal to the delay introduced by said means for reproducing the propagation delays of the output pre-buffers, so as to update the configuration of said output pre-buffers in the time interval determined by said synchronous pulse.

6 more elements

A memory device including a memory matrix;

an internal bus for the transfer of data and reporting signals from and to the memory matrix;
output pre-buffers for the transfer of data to output terminals of the memory matrix;
and
a pulse generation circuit for the synchronized loading of data in an output pre-buffer, further comprising a synchronization circuit;
a transmission path delay reproduction circuit which reproduces propagation delays of the data transmitted to said output terminals;
and a pre-buffer delay reproduction circuit which reproduces the propagation delays of said output pre-buffers;
said synchronization circuit synchronizes the generation of at least one pulse that is synchronized with the propagation delays reproduced by said transmission path reproduction circuit, said pulse enabling the loading of the data in said output pre-buffers, said synchronization being provided as a consequence of the assured presence of the data, said synchronous pulse being restored after a time that is equal to the delay introduced by said means for reproducing the propagation delays of the output pre-buffers, so as to update the configuration of said output pre-buffers in the time interval determined by said synchronous pulse.

4 more elements

Dependencies are inferred from the claim text.

Pulse generation circuit and method for synchronized data loading in an output pre-buffer

Life of this patent

Pulse generation circuit and method for synchronized data loading in an output pre-buffer

Life of this patent

Abstract

Claims38