Semiconductor integrated circuit device having a controlled overdriving circuit

A semiconductor memory comprising:

• first and second power supply terminals;
• first and second power supply lines, each of which has a first end coupled to the corresponding one of said first and second power supply terminals and extends in the same direction as each other;
• first and second memory blocks, each of which comprises a plurality of pairs of bit lines, a plurality of word lines, a plurality of dynamic memory cells and a plurality of sense amplifiers coupled to said plurality of pairs of bit lines, respectively, wherein each of said plurality of sense amplifiers includes a pair of PMOS transistors and a pair of NMOS transistors, and wherein each of said pairs of PMOS and NMOS transistors has sources coupled in common, drains coupled to the corresponding pair of bit lines, respectively, and gates cross-coupled to said drains, respectively;
• a first switch transistor coupled between a first portion of said first power supply line and said sources of pairs of said PMOS transistors in said first memory block;
• a second switch transistor coupled between a second portion of said second power supply line and said sources of said pairs of PMOS transistors in said first memory block;
• a third switch transistor coupled between a third portion of said first power supply line and said sources of said pairs of PMOS transistors in said second memory block;
• a fourth switch transistor coupled between a fourth portion of said second power supply line and said sources of said pairs of PMOS transistors in said second memory block;
• and
• a voltage generator for providing said first power supply terminal with a first voltage which is lower than a second voltage supplied to said second power supply terminal,
• wherein said first portion of said first power supply line is located between said third portion of said first power supply line and said first power supply terminal,
• wherein said second portion of said second power supply line is located between said fourth portion of said power supply line and said second power supply terminal,
• wherein each of said sense amplifiers in said first memory block provides the corresponding pair of bit line with a pair of first complementary signals having a high side voltage and a low side voltage on the basis of information stored in a memory cell selected from said plurality of dynamic memory cells in said first memory block,
• wherein, in a first period, said high side voltage of said pair of first complementary signals is raised over said first voltage in response to said second switch transistor being enabled, and
• wherein, in a second period following said first period, said high side voltage of said pair of first complementary signals is lowered in response to said first switch transistor being enabled so that said high side voltage is set to said first voltage.

In an integrated circuit having an amplifier circuit, a method for driving a data signal to the amplifier circuit at a desired level comprising:

• providing an enable circuit for generating a first and second enable signal;
• overdriving the data signal with an overdrive voltage for a first period;
• driving the data signal with a second voltage for a second period, wherein the second voltage pulls the data signal to the desired level;
• wherein the first period is initiated by the first enable signal and the second period is initiated by the second enable signal and a length of the first period is responsive to the location of the enable circuit relative to the amplifier circuit.

A method for driving first and second signals of an integrated circuit to a desired voltage level comprising:

• providing an overdrive voltage at a level that exceeds the desired voltage level and a second voltage at the desired voltage level;
• overdriving the first signal with an overdrive voltage for a first period;
• overdriving the second signal with the overdrive voltage for a second period;
• driving the first signal with a second voltage for a third period;
• and
• driving the second signal with the second voltage for a fourth period.

An apparatus for driving a data signal in an integrated circuit to a desired level comprising:

• a first circuit for overdriving the data signal with an overdrive voltage for a first period;
• a second circuit for driving the data signal with a second voltage for a second period to pull the data signal to the desired level;
• and
• an enable circuit for generating a first and second enable signal wherein the first enable signal initiates the first period and the second enable signal concludes the first period and initiates the second period and wherein the timing of the generation of the second enable signal is responsive to the distance between the location of the enable circuit and the location of the data circuitry.

A circuit for driving first and second signals to a desired level comprising:

• means for providing an overdrive voltage at a level that exceeds the desired voltage level, and a second voltage at a second voltage level;
• means for overdriving the first signal with an overdrive voltage for a first period;
• means for overdriving the second signal with the overdrive voltage for a second period;
• means for driving the first signal with a second voltage for a third period;
• and
• means for driving the second signal with the second voltage for a fourth period;
• wherein the second voltage pulls the first and second signals to the desired level.

A dynamic random access memory structure comprising:

• means for supplying a VDD voltage level;
• means for supplying a VSS voltage level;
• a voltage circuit for supplying a V1 voltage level;
• a first bit line having a first voltage level signal thereon;
• a second bit line having a second voltage level signal thereon;
• a first sense amplifier circuit connected to the first bit line for driving the first voltage signal to the V1 voltage level;
• a second sense amplifier circuit connected to the second bit line for driving the second voltage signal to the V1 voltage level;
• a control circuit comprising:
• means for overdriving the first sense amplifier with the VDD voltage level for a first period;
• means for overdriving the second sense amplifier with the VDD voltage level for a second period;
• means for driving the first bit line with the V1 voltage level for a third period;
• and
• means for driving the second bit line with the V1 voltage level for a fourth period,
• wherein the voltage level signals on first and second bit lines are driven past the V1 voltage level during the first and second period, and to the V1 voltage level during the third and fourth period.

A semiconductor memory comprising:

• first and second power supply terminals;
• first and second power supply lines, each of which has a first end coupled to the corresponding one of said first and second power supply terminals and extends in the same direction as each other;
• first and second memory blocks, each of which comprises a plurality of pairs of data lines, a plurality of word lines, a plurality of dynamic memory cells and a plurality of sense amplifiers coupled to said plurality of pairs of bit lines, respectively, wherein each of said plurality of sense amplifiers includes a pair of PMOS transistors and a pair of NMOS transistors, and wherein each of pairs of PMOS and NMOS transistors has sources coupled in common, drains coupled to the corresponding pair of bit lines, respectively, and gates cross-coupled to said drains, respectively;
• a first switch transistor coupled between a first portion of said first power supply line and said sources of pairs of PMOS transistors in said first memory block;
• a second switch transistor coupled between a second portion of said second power supply line and said sources of said pairs of PMOS transistors in said first memory block;
• a third switch transistor coupled between a third portion of said first power supply line and said sources of said pairs of PMOS transistors in said second memory block;
• a fourth switch transistor coupled between a fourth portion of said second power supply line and said sources of said pairs of PMOS transistors in said second memory block;
• a first signal line which has a first end coupled to a first signal terminal and extends in the same direction as said first and second power supply lines;
• a first control circuit, coupled to a fifth portion of said first signal line, controlling said first and second switches;
• and
• a second control circuit, coupled to a sixth of said first control signal line, controlling said third and fourth switches,
• wherein a first voltage supplied to said first power supply terminal is lower than a second voltage supplied to said second power supply terminal,
• wherein said first portion of said first power supply line is located between said third portion of said first power supply line and said first power supply terminal,
• wherein said second portion of said second power supply line is located between said forth portion of said second power supply line and said second power supply terminal,
• wherein said fifth portion of said first signal line is located between said sixth portion of said first signal line and said first signal terminal,
• wherein each of said sense amplifiers provides the corresponding pair of bit lines with a pair of first complementary signals having a high side voltage and a low side voltage on the basis of information stored in a memory cell selected from said plurality of dynamic memory cells,
• wherein said second switch transistors is enabled in a first period, and said first switch transistor is enabled in a second period following to said first period, and
• wherein said fourth switch transistor is enabled in a third period, and said third switch transistor is enabled in a fourth period following to said third period.