Semiconductor memory device and computer

A semiconductor memory device comprising:

• a memory cell array having a plurality of memory cells;
• a data output line pair receiving potentials being in a range from a first potential to a second potential higher than said first potential and corresponding to data stored in the memory cell selected in accordance with an address signal from said plurality of memory cells in said memory cell array, and producing a potential difference between one of said potentials and the other of the same;
• precharge means receiving a precharge signal for setting said data output line pair to a precharge potential higher than said first potential and lower than said second potential in accordance with said precharge signal;
• differential amplifier means receiving one and the other of said potentials of said data output line pair and for amplifying the potential difference on said data output line pair for outputting amplified signals;
• and
• output fixing signal generating means receiving said amplified signals from said differential amplifier means and outputting an output fixing signal attaining a predetermined level in response to one of said amplified signals attaining the H-level and the other attaining the L-level.

A semiconductor memory device comprising:

• a plurality of memory cells;
• an access request signal terminal receiving an access request signal;
• a busy signal terminal;
• a data output terminal;
• a valid data signal terminal;
• and
• means for outputting a busy signal to said busy signal terminal, the busy signal being set to one level indicating a busy state in response to the access request signal designating that an access of said semiconductor memory device is requested, said means for outputting data from one of said memory cells corresponding to an address signal to said data output terminal, and for outputting a valid data signal to said valid data signal terminal, the valid data signal being set to one level indicating that data outputted to said data output terminal is valid.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells;
• a data output terminal;
• output means for outputting data from said memory cell array to said data output terminal;
• a valid signal terminal;
• and
• a valid data signal generator configured to generate a valid data signal designating when the data at said data output terminal is valid and apply said valid data signal to the valid data signal terminal.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells;
• a data output terminal;
• output means for outputting data from said memory cell array to said data output terminal;
• and
• a valid signal terminal providing a valid data signal outside the semiconductor memory device designating when data at the data output terminal is valid.