Flexible fuse placement in redundant semiconductor memory
AssigneeSiemens Aktiengesellschaft
InventorPeter Poechmueller
Life of this patent
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Abstract
Disclosed is a semiconductor memory having a main memory cell array and redundant memory cells, with a plurality of fuses that can be physically separated from their associated fuse latches. Physical separation is possible by incorporating serial transfer circuitry to serially transfer fuse data from the fuses towards the latches. As a result, only a small number of wires are needed to connect the fuses to the fuse latches, allowing for flexible fuse placement within the memory.
Claims22
A semiconductor memory having a main memory cell array and redundant memory cells, said memory comprising:
- a plurality of fuses for storing address information, each fuse being in either an open or closed state corresponding to a bit of an address of at least one faulty cell within said main memory cell array;
- a plurality of latches for storing the address information stored in said fuses during operation of said semiconductor memory to facilitate storage of data in said redundant memory cells as a substitute for faulty cells in said main memory cell array;
- and
- serial transfer circuitry operable to serially transfer at least some of said address information from said fuses towards said latches.
A random access memory (RAM) having a plurality of memory blocks, each memory block including a main memory cell array and redundant memory cells, said RAM comprising:
- a plurality of fuse banks each associated with one of said memory blocks and each including plural fuses for storing address information, each fuse being in either an open or closed state corresponding to a bit of an address of at least one faulty cell within said main memory cell array;
- a plurality of fuse latch sections, each including a plurality of fuse latches for storing the address information stored in one of said fuse banks during operation of said RAM to facilitate storage of data in said redundant memory cells as a substitute for faulty cells in said main memory cell array;
- at least one first shift register in proximity to said fuses of at least one of said fuse banks;
- at least one second shift register in proximity to at least one fuse latch section;
- a plurality of switches coupled between fuses of one of said fuse banks and at least one bus line, said switches being sequentially closed by said first shift register to serially transfer fuse data onto said bus line, said second shift register sequentially activating latch set inputs of said latches to sequentially transfer said fuse data from said at least one bus line to said latches;
- and
- logic circuitry coupled to said first and second registers to synchronize said registers to one another and control timing of fuse data transfer.
In a semiconductor memory having a main memory cell array, redundant memory cells for data storage in place of faulty cells of said main memory cell array, a plurality of fuses for storing address information indicative of a faulty cell or a group of cells containing a faulty cell, and a plurality of fuse latches for storing the address information of said fuses during operation of said semiconductor memory, a method for transferring the address information from said fuses to said latches, comprising:
- providing at least one bus line between said plurality of fuses and said plurality of latches;
- and
- serially transferring at least some of said address information from said fuses towards said latches on said at least one bus line.
Dependencies are inferred from the claim text.