Data holding circuit and buffer circuit

A data holding circuit comprising:

• first and second clock terminals receiving clock signals which have logical levels in mutually exclusive relation;
• first and second field effect transistors of a first conductivity type having control terminals connected to said second clock terminal, and first current electrodes connected to first and second signal input lines receiving input signals, respectively;
• third and fourth field effect transistors of said first conductivity type having control terminals connected to said first clock terminal, and first current electrodes connected to second current electrodes of said first and second field effect transistors, respectively;
• a first signal inverting circuit having an input terminal connected to said second current electrode of said second field effect transistor, and an output terminal connected to a second current electrode of said third field effect transistor and a first signal output line outputting a signal;
• a second signal inverting circuit having an input terminal connected to said second current electrode of said first field effect transistor, and an output terminal connected to a second current electrode of said fourth field effect transistor and a second signal output line outputting a signal;
• and
• a fifth field effect transistor of a second conductivity type having a control terminal connected to said input terminal of said second signal inverting circuit, a first current electrode connected to said input terminal of said first signal inverting circuit, and a second current electrode provided a potential so that said first and second electrodes of said fifth field effect transistor are drain and source electrodes, respectively.

A data holding circuit comprising:

• first and second clock terminals receiving clock signals which have logical levels in mutually exclusive relation;
• first and second field effect transistors of a first conductivity type having control terminals connected to said second clock terminal, and first current electrodes connected to first and second signal input lines receiving input signals, respectively;
• third and fourth field effect transistors of said first conductivity type having control terminals connected to said first clock terminal, and first current electrodes connected to second current electrodes of said first and second field effect transistors, respectively;
• a first signal inverting circuit having an input terminal connected to said second current electrode of said second field effect transistor, and an output terminal connected to said second current electrode of said third field effect transistor;
• a second signal inverting circuit having an input terminal connected to said second current electrode of said first field effect transistor, and an output terminal connected to said second current electrode of said fourth field effect transistor;
• a fifth field effect transistor of a second conductivity type having a control terminal connected to said input terminal of said second signal inverting circuit, a first current electrode connected to said input terminal of said first signal inverting circuit, and a second current electrode provided a potential so that said first and second electrodes of said fifth field effect transistor are drain and source electrodes, respectively;
• a sixth field effect transistor of said second conductivity type having a control terminal connected to said input terminal of said first signal inverting circuit, a first current electrode connected to said input terminal of said second signal inverting circuit, and a second current electrode provided a potential so that said first and second electrodes of said sixth field effect transistor are drain and source electrodes, respectively;
• seventh and eighth field effect transistors of said first conductivity type having control terminals connected to said first clock terminal, and first current electrodes connected to said output terminals of said first and second signal inverting circuits, respectively;
• ninth and tenth field effect transistors of said first conductivity type having control terminals connected to said second clock terminal, and first current electrodes connected to second current electrodes of said seventh and eighth field effect transistors, respectively;
• a third signal inverting circuit having an input terminal connected to said second current electrode of said eighth field effect transistor, and an output terminal connected to a second current electrode of said ninth field effect transistor;
• a fourth signal inverting circuit having an input terminal connected to said second current electrode of said seventh field effect transistor, and an output terminal connected to a second current electrode of said tenth field effect transistor;
• an eleventh field effect transistor of said second conductivity type having a control terminal connected to said input terminal of said fourth signal inverting circuit, a first current electrode connected to said input terminal of said third signal inverting circuit, and a second current electrode provided a potential so that said first and second electrodes of said eleventh field effect transistor are drain and source electrodes, respectively;
• and
• a twelfth field effect transistor of said second conductivity type having a control terminal connected to said input terminal of said third signal inverting circuit, a first current electrode connected to said input terminal of said fourth signal inverting circuit, and a second current electrode provided a potential so that said first and second electrodes of said twelfth field effect transistor are drain and source electrodes, respectively.