Semiconductor memory device including internal power supply circuit generating a plurality of internal power supply voltages at different levels

A semiconductor memory device comprising:

• a plurality of internal power supply circuits for generating a plurality of internal power supply voltages at different voltage levels, respectively;
• a memory cell array having a plurality of memory cells arranged in rows and columns;
• a plurality of bit line pairs arranged corresponding to said columns and connected to the memory cells on the corresponding columns, respectively;
• a plurality of word lines arranged corresponding to said rows and connected to the memory cells on the corresponding rows, respectively;
• a plurality of sense amplifiers arranged corresponding to said plurality of bit line pairs for differentially amplifying potentials on the corresponding bit line pairs when made active, each of said sense amplifiers including a circuit portion for transmitting a first internal power supply voltage generated from a first internal power supply circuit included in said plurality of internal power supply circuits to a bit line of a corresponding bit line pair at a higher potential when activated;
• column select means for generating a column select signal selecting an addressed column among said plurality of columns in accordance with an address signal, said column select means including means for generating the column select signal at a level of said first internal power supply voltage;
• a column select gate for electrically coupling, in accordance with said column select signal, the bit line pair arranged corresponding to the addressed column to an internal data line pair;
• and
• a peripheral circuit receiving a second internal power supply voltage higher than said first internal power supply voltage as one operation power supply voltage thereof, and performing an operation related at least to row selection for said plurality of rows in accordance with an externally applied signal.