Read circuit for non-volatile memory working with a low supply voltage
AssigneeSGS-Thomson Microelectronics S.A.
InventorEmilio Miguel Yero
Life of this patent
Estimating the term…
Abstract
The memory, in integrated circuit form, is supplied with a low supply voltage and includes a read circuit enabling the detection of the state of the cells of the memory. In a current mirror of the read circuit, there is provided a shifting circuit between the drain and the gate of a reference transistor. The shifting circuit may include a shift transistor and a bias transistor.
Claims23
A memory integrated circuit comprising:
- a plurality of memory cells;
- at least one bit line and one reference line connected to said memory cell;
- and
- a read circuit comprising
- pre-charging means for pre-charging the at least one bit line and the reference line responsive to a pre-charging signal,
- a current mirror to supply current to the at least one bit line and the reference line, said current mirror comprising a reference transistor and a mirror transistor, the reference transistor and the mirror transistor having respective gates connected to each other, the reference transistor and mirror transistor having respective sources connected to a supply, the reference transistor having a drain connected to the pre-charging means, and the mirror transistor having a drain connected to the reference line,
- a differential amplifier connected to said current mirror, and
- shifting means connected between the drain and gate of the reference transistor for shifting a potential of the drain of the reference transistor with a shifting voltage and applying the resulting potential to the gate of the reference transistor.
A memory integrated circuit comprising:
- a plurality of memory cells;
- at least one bit line and one reference line connected to said memory cell;
- and
- a read circuit comprising
- pre-charging means for pre-charging the at least one bit line and the reference line,
- a current mirror to supply current to the at least one bit line and the reference line, said current mirror comprising a reference transistor and a mirror transistor, the reference transistor and the mirror transistor having respective gates connected to each other, the reference transistor and mirror transistor having respective sources connected to a supply, the reference transistor having a drain connected to said pre-charging means, and the mirror transistor having a drain connected to the reference line, and
- shifting means connected between the drain and the gate of the reference transistor for shifting a potential of the drain of the reference transistor with a shifting voltage and applying the resulting potential to the gate of the reference transistor.
A memory read circuit comprising:
- pre-charging means for pre-charging at least one bit line and reference line;
- a current mirror to supply current to the at least one bit line and reference line, said current mirror comprising a plurality of transistors;
- and
- shifting means for shifting a potential to at least one of said plurality of transistors of said current mirror.
A method for reading a memory of a type comprising a plurality of memory cells, at least one bit line and one reference line connected to said memory cell, and a read circuit comprising pre-charging means for pre-charging the at least one bit line and the reference line, and a current mirror to supply current to the at least one bit line and the reference line, said current mirror comprising a reference transistor and a mirror transistor, the reference transistor and the mirror transistor having respective gates connected to each other, the reference transistor and mirror transistor having respective sources connected to a supply, the reference transistor having a drain connected to said pre-charging means, and the mirror transistor having a drain connected to the reference line, the method comprising the step of:
- shifting a potential of the drain of the reference transistor with a shifting voltage and applying the resulting potential to the gate of the reference transistor.
Dependencies are inferred from the claim text.