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AssigneeSGS-Thomson Microelectronics S.A.
InventorsMarco Maccarrone, Jacopo Mulatti, Carla Maria Golla
Estimating the term…
A circuit for generating biasing signals in reading of a redundant UPROM cell incorporating at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, as well as MOS transistors connecting the memory element with a reference low supply voltage comprises a voltage booster for generating a first voltage output signal to be applied to the control terminal of the memory element and a limitation network for the voltage signal connected to the output of the voltage booster. There is also provided a circuit portion for generating a second voltage output signal to be applied to the control terminal of one of the above mentioned transistors. This circuit portion comprises a timing section interlocked with the voltage booster of a section generating the second voltage signal.
A circuit for generating biasing signals for reading a redundant UPROM cell including at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, and MOS transistors connecting said memory element with a reference low supply voltage, said circuit comprising:
A circuit for generating biasing signals for reading a redundant UPROM cell including at least one memory element of the EPROM or flash type and having a control terminal and a conduction terminal to be biased, and MOS transistors connecting said memory element with a reference low supply voltage, said circuit comprising:
Dependencies are inferred from the claim text.