Programming of memory cells using connected floating gate analog reference cell
AssigneeAdvanced Micro Devices, Inc.
InventorLee Cleveland
Life of this patent
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Abstract
A reference cell (114) has a "floating gate" (116) that is tied to a voltage reference (118) in emulation of a programmed cell. An associated programming method is used which compares the voltage of a node (112) associated with the cell (114) with the voltage on a similar node (108) associated with a selected cell (12) in the array; the array cell (12) is determined to be sufficiently programmed when a predetermined relationship is obtained between these two nodes. In this manner, a separate verify mode is avoided.
Claims11
Apparatus for determining when a selected electrically programmable memory cell in an array of such cells has been programmed, comprising:
- a reference cell having structural characteristics which are substantially similar to said selected cell;
- a floating gate analog of said reference cell coupled to a voltage reference, the value of said voltage reference preselected to cause said analog to emulate a floating gate of said selected cell as it would exist in a programmed condition;
- a voltage comparator having first and second inputs, circuitry for coupling a predetermined structural component of said reference cell to said first input of said voltage comparator;
- circuitry for coupling a structural component corresponding of the selected cell to said structural component of said reference cell to said second input of said voltage comparator;
- and
- an output of the voltage comparator for indicating that the selected cell is programmed responsive to the voltage on said second input of said voltage comparator having a value at least as large as the voltage appearing on said first input of said voltage comparator.
An electrically erasable and programmable (EEPROM) memory, comprising:
- an array of memory cells, each cell in said array having a floating gate and a second predetermined structural component;
- a reference cell having a floating gate analog and a second predetermined structural component, said second predetermined structural component and said floating gate analog of said reference cell being respectively similar in structure to the second predetermined structural components and floating gates of said cells in said array;
- a voltage reference connected to said floating gate analog, the value of said voltage reference preselected to emulate a floating gate of a cell in said array as it would exist in a programmed condition;
- and
- a voltage comparator, a first input of said voltage comparator selectively coupled to said second predetermined structural component of a selected cell to be programmed in said array, a second input of said voltage comparator coupled to said second predetermined structural component of said reference cell, an output of said voltage comparator declaring said selected cell as programmed when the voltage on said first input is in a predetermined relationship with the voltage on said second input of said comparator.
A method of programming a selected cell in an array of electrically programmable memory cells, comprising the steps of:
- coupling a structural component of a reference cell exhibiting the characteristics of a programmed memory cell to a first input of a voltage comparator;
- coupling a like structural component of the selected cell to a second input of a voltage comparator;
- beginning the application of a programming voltage to a control gate of the selected cell;
- and
- continuing to apply the programming voltage to the control gate of the selected cell until the voltage on the first input is in a predetermined relationship to the voltage appearing on the second input.
Dependencies are inferred from the claim text.