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US 5,859,795 AGranted
Multi-level memory circuits and corresponding reading and writing methods
AssigneeSGS-Thomson Microelectronics S.A.
InventorPaolo Rolandi
Life of this patent
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Abstract
The present invention relates to a memory circuit of the multi-level type, i.e. a memory circuit having a plurality of memory elements, each adapted to store more than one binary information unit, wherein the memory elements are utilized for storing a number of binary information units tied to an acceptable error rate for a particular application: typically, one bit where a low error rate is sought, and two bits where a higher error rate can be accepted.
Claims19
A memory circuit comprising:
- a plurality of memory elements, each capable of storing a multiplicity of binary information units, said plurality of memory elements having at least first and second modes of operation, the memory elements being utilized in said first mode of operation as if adapted for storing each a first number of binary information units, and being utilized in said second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation,
- at least two input/output terminals;
- a multiplexer connected to said input/output terminals;
- and
- a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.
2 more elements
A memory circuit comprising:
- a plurality of memory elements divided into at least a first set and a second set, memory elements in said first set being utilized in a first mode of operation as if adapted for storing each a first number of binary information units, and memory elements in said second set being utilized in a second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation,
- at least two input/output terminals;
- a multiplexer connected to said input/output terminals;
- and
- a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.
2 more elements
A semiconductor integrated electronic storage device comprising:
- at least one memory circuit, said at least one memory circuit comprising a plurality of memory elements, each capable of storing a multiplicity of binary information units, said plurality of memory elements having at least first and second modes of operation, the memory elements being utilized in said first mode of operation as if adapted for storing each a first number of binary information units, and being utilized in said second mode of operation as if adapted for storing each a second number of binary information units, said first and second numbers being dissimilar, said numbers chosen to have at least a two-level and multi-level mode of operation,
- at least two input/output terminals;
- a multiplexer connected to said input/output terminals;
- and
- a control unit connected to said multiplexer and operative to enable said modes of operation in relation to incoming selection instructions, wherein data in one mode can be obtained from data in the other mode.
2 more elements
Dependencies are inferred from the claim text.