Multilevel memory cell sense amplifier system and sensing methods

A dynamic memory circuit comprising:

• a plurality of dynamic memory cells each capable of storing one of four signal values representative of two binary bits of data;
• a first sense amplifier coupled to said plurality of memory cells, said first sense amplifier detecting a binary value of a first bit of said two binary bits of data stored in a selected memory cell;
• a second sense amplifier coupled to said plurality of memory cells, said second sense amplifier detecting a binary value of a second bit of said two binary bits of data stored in the selected memory cell;
• and
• a restore circuit coupled to receive said binary value of said first bit at a first input and said binary value of said second bit at a second input, said restore circuit controlling a restore operation of the dynamic memory circuit in response to the binary values of said first and second bits.

A method of operating a dynamic memory circuit capable of storing two bits of data per memory cell, comprising the steps of:

• generating a first voltage differential on a bit line by selecting a memory cell coupled thereto;
• detecting the binary value of a first bit of data stored in said memory cell by sensing said voltage differential using a first sense amplifier;
• coupling feedback charge to either a first or a second sense node of a second sense amplifier in response to the binary value of said first bit of data, thereby generating a second voltage differential;
• and
• detecting the binary value of a second bit of data by sensing said second voltage differential using said second sense amplifier.

A method of operating a dynamic memory circuit capable of storing two bits of data per memory cell, comprising the steps of:

• generating a first voltage differential on a bit line by accessing a memory cell coupled thereto;
• detecting the binary value of a first bit of data stored in said memory cell by sensing said first voltage differential using a first sense amplifier;
• generating a second voltage differential in response to the binary value of said first bit of data;
• detecting the binary value of a second bit of data by sensing said second voltage differential using a second sense amplifier;
• and
• comparing the binary values of said first and second bits of data in order to restore the content of said memory cell.

A DRAM memory comprising:

• a plurality of memory cells, each memory cell being capable of storing two bits of information, a first bit and a second bit;
• a first sense amplifier for reading out from any one of said plurality of memory cells the state of said first bit;
• a second sense amplifier for reading out from said one of said plurality of memory cells the state of said second bit;
• a first pair of data leads adapted to send to and receive from said first sense amplifier a first pair of signals representing said first bit and the complement of said first bit;
• a second pair of data leads adapted to send to and receive from said second sense amplifier a second pair of signals representing said second bit and the complement of said second bit;
• and,
• circuitry for writing into a selected one of said plurality of memory cells a signal representing said first bit and said second bit, including:
• a bit line adapted to receive the signal representing said first bit from said first sense amplifier;
• a reference bit line adapted to receive the signal representing the complement of said first bit from said first sense amplifier;
• an exclusive OR gate adapted to receive said pair of signals representing said first bit and the complement of said first bit and to receive said pair of signals representing said second bit and the complement of said second bit and to produce a signal representing the exclusive "OR" of said first bit and said second bit;
• a first transistor switch for dividing the reference bit line into two parts;
• a second transistor switch, capable of connecting said bit line to one of the two parts of said reference bit line;
• and
• a restore signal line connected so that when the restore signal is high and the exclusive "OR" output signal is high, the second transistor switch is "ON" and the bit line is connected to said one part of the reference bit line and so that when the restore signal is high and the exclusive "OR" output signal is not high the second transistor switch is "OFF" and the bit line is not connected to said one part of the reference bit line.

A method of processing data in a DRAM, the method comprising:

• connecting a first node of a first sense amplifier to a bit line;
• connecting a second node of the first sense amplifier to a reference bit line;
• connecting a first node of a second sense amplifier to said bit line;
• and
• connecting a second node of the second sense amplifier to said reference bit line;
• connecting a reference voltage source to the bit line and to the reference bit line and then disconnecting the reference voltage source to leave the reference voltage on the bit line and on the reference bit line;
• selecting a memory cell capacitor having a voltage stored therein, said stored voltage being one of a set consisting of V.sub.00, V.sub.01, V.sub.10 and V.sub.11, where V.sub.00 and V.sub.01 are less than the reference voltage, V.sub.10 and V.sub.11 are greater than the reference voltage, V.sub.00 is less than V.sub.01, and V.sub.10 is less than V.sub.11 ;
• accessing the selected memory cell capacitor by connecting the selected memory cell capacitor to the bit line to change the bit line voltage by delta V, where delta V, a certain fraction of the stored voltage, is one of a set consisting of delta V.sub.00, delta V.sub.01, delta V.sub.10, and delta V.sub.11 corresponding to V.sub.00, V.sub.01, V.sub.10, and V.sub.11, respectively, where delta V.sub.00 and delta V.sub.01 are negative, delta V.sub.10 and delta V.sub.11 are positive, delta V.sub.01 is greater than delta V.sub.00, and delta V.sub.11 is greater than delta V.sub.10 ;
• disconnecting the second sense amplifier from the bit line and from the reference bit line;
• activating the first sense amplifier to produce a first output bit having one of the values "0" and "1", where a first bit output value "0" indicates negative delta V and indicates that the stored voltage on the accessed capacitor was one of the set of voltages V.sub.00 and V.sub.01 that are less than the reference voltage, and where a first bit value "1" indicates positive delta V and indicates that the stored voltage on the accessed capacitor was one of the set of voltages V.sub.10 and V.sub.11 that are greater than the reference voltage;
• allowing the voltages on the bit line and on the reference bit line to follow the state of the first sense amplifier so that for a first bit value "1" the bit line goes to Vcc and the reference bit line goes to ground and so that for a first bit value "0" the bit line goes to ground and the reference bit line goes to Vcc;
• applying the state of the first sense amplifier to a feedback structure to change the voltage difference between the first and second nodes in the second sense amplifier, for first bit value "0", from delta V.sub.00 to (delta V.sub.00 +delta V.sub.FB) and from delta V.sub.01 to (delta V.sub.01 +delta V.sub.FB), and for first bit value "1", from delta V.sub.10 to (delta V.sub.10 -delta V.sub.FB) and from delta V.sub.11 to (delta V.sub.11 -delta V.sub.FB), where delta V.sub.FB is intermediate in value between delta V.sub.10 and delta V.sub.11 and intermediate in value between the magnitude of delta V.sub.00 and the magnitude of delta V.sub.01 so that (delta V.sub.00 +delta V.sub.FB) is negative, (delta V.sub.01 +delta V.sub.FB) is positive, (delta V.sub.10 -delta V.sub.FB) is negative, and (delta V.sub.11 -delta V.sub.FB) is positive;
• and
• activating the second sense amplifier to produce a second output bit having values "0" for stored voltage V.sub.00, "1" for stored voltage V.sub.01, "0" for stored voltage V.sub.10, and "1" for stored voltage V.sub.11.

A method of restoring data to a DRAM cell capacitor comprising part of a memory circuit capable of storing two bits of information in each cell, said memory circuit including a bit line and a reference bit line, a first sense amplifier and a second sense amplifier, the method comprising:

• outputting a first bit from the first sense amplifier and a second bit from the second sense amplifier and forming a signal representing the exclusive "OR" of the first bit and the second bit;
• applying a signal to divide the reference bit line in half;
• applying the exclusive "OR" signal so that when the value of the first bit is "1" and the value of the second bit is "0," the bit line is shorted to one half of the reference bit line to provide a voltage approximately equal to 2/3 Vcc, and so that when the value of the first bit is "0" and the value of the second bit is "1" the bit line is shorted to said one half of the reference bit line to provide a voltage approximately equal to 1/3 Vcc;
• and
• changing the voltage on a word line to isolate the cell capacitor from the bit line after the appropriate charge has been restored on the DRAM cell capacitor.