Content addressable memory
AssigneeNorthern Telecom Limited
InventorsKenneth James Schultz, Garnet Frederick Randall Gibson, Farhad Shafai, Armin George Bluschke
Life of this patent
Estimating the term…
Abstract
The implementation of two-dimensional decoding, necessary to achieve a reasonable array aspect ratio for a large content addressable memory, is achieved by having multiple match lines per physical row, these match lines being physically routed on top of the array core cell in an upper metal layer. To limit power dissipation in the resulting large-capacity content addressable memory, the match function is implemented by two or more NAND chains per word. Means for achieving the precharging and evaluation of these chains, and for implementing dummy chains for the provision of timing information, are also disclosed.
Claims36
A content addressable memory (CAM) with w rows.times.b columns comprising:
- w words of matching means, each word comprising i segmented match line chains, each match line chain comprising b/i core cells which are chained by a match line, each core cell comprising means for storing data, w, i and b being integers;
- logic means for logically coupling the match line chains in a respective row;
- and
- encoding means for providing search results based on the outputs from the logic means.
A dummy match line chain for use in a CAM comprising an array of data store cells coupled with bit lines, the dummy match line chain comprising CAM cells.
A core cell comprises:
- first and second N-channel FETs and first and second P-channel FETs forming two cross-coupled inverters for storing differential data;
- third and fourth N-channel FETs coupled with the differential data nodes to differential bit lines, the FETs being gated by a word line, so as to provide access for read and write data operations;
- a fifth N-channel FET;
- sixth and seventh N-channel FETs, either of them being gated by the positive storage node and for connecting a positive comparison bit line to the gate of the fifth N-channel FET, the other being gated by the negative storage node and for connecting a negative comparison bit line to the gate of the fifth N-channel FET, the comparison bit lines being physically distinct from the bit lines employed for read and write access, the source and drain of the fifth N-channel FET being connected to those of neighbouring cells to form a chain of such FETs.
Dependencies are inferred from the claim text.