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US 5,859,776 AGranted
Method and apparatus for the design of a circuit
AssigneeSony Corporation
InventorsKenichi Sato, Norihisa Shirota, Yasuhiro Iida, Mitsuru Sasano
Life of this patent
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Abstract
In automated design, a useful insertion of a delay buffer or an increase in the delay time of the critical path could not been prevented. When inserting a logic element between two certain points on the circuit, substitution of other paths passing through the relevant insertion position is considered and the insertion position of the logic element is determined finally.
Claims20
A method for the design of a circuit for a logic design, comprising the steps of:
- receiving circuit information concerning a circuit to be designed;
- receiving hold time violation path information concerning paths on said circuit having a hold time greater than a predetermined time;
- and
- determining an insertion position where a logic element is inserted between certain two points on said circuit on the basis of said circuit information and said hold time violation path information, wherein
- said determining step determines said insertion position by taking into consideration a delay of other paths through the insertion position of said logic element.
2 more elements
An apparatus for the design of a circuit, comprising:
- means for receiving circuit information concerning a circuit to be designed;
- means for receiving hold time violation path information concerning paths on said circuit having a hold time greater than a predetermined time;
- means for determining an insertion position where logic element is inserted between certain two points on said circuit on the basis of said circuit information and said hold time violation path information;
- and wherein
- said determining means determines said insertion position by taking into consideration a delay of other paths through the insertion position of said logic element.
2 more elements
A method for the design of a circuit for a logic design, comprising the steps of:
- receiving circuit information from a circuit to be designed to determine a delay time in each path of said circuit;
- summing the delay times of each path to determine a maximum delay time;
- receiving hold time violation path information from a path in said circuit having a hold time greater than a predetermined time;
- evaluating the effect of an insertion of a delay element for a plurality of input pins present on the path having a hold time greater than a predetermined time, wherein the circuit comprises a plurality of cells and each of the plurality of cells includes a plurality of input pins;
- selecting a delay element insertion position before one of the plurality of input pins based on the circuit information and the hold time violation path information by taking into consideration a delay of other paths through the delay element insertion position such that the delay element insertion position selected is a most efficient delay element insertion position;
- and
- inserting the delay element into the delay element insertion position.
4 more elements
Dependencies are inferred from the claim text.