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US 5,859,633 AGranted
Gradation driving circuit of liquid crystal display
AssigneeLG Electronics Inc.
InventorJun-Hee Kim
Life of this patent
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AssigneeLG Electronics Inc.
InventorJun-Hee Kim
Estimating the term…
A gradation driving circuit is provided that outputs gamma-corrected gray scale voltages. First and second multiplexors select first and second source voltages, respectively, in response to input data. The first source voltage is scaled by an appropriate factor corresponding to a required amount of gamma correction. The scaling factor is selected based on an additional output from the second multiplexor. The scaled first voltage is then subtracted from the second source voltage and the difference is output as the gray scale voltage. Alternatively, the gray scale voltage can be obtained by adding the first scaled source voltage and the second source voltage.
An electronic circuit for outputting a drive voltage comprising:
An electronic circuit for outputting a drive voltage comprising:
An electronic circuit for outputting a drive voltage comprising:
An electronic circuit for outputting a drive voltage comprising:
An electronic circuit for outputting a drive voltage comprising:
A gradation driving circuit of a liquid crystal display, comprising:
A gradation driving circuit of a liquid crystal display, comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
Display of intermediate tones: by amplitude modulation
Details of drivers for data electrodes: suitable for active matrices only
Control of matrices with row and column drivers: using an active matrix
Details of driving circuits: details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
Term ended 20 Feb 2017 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to a thin film transistor (TFT) liquid crystal display (LCD) and, more particularly to a gradation driving circuit which can output a large number of gray scale voltages in response to a minimum number of input voltages.
2. Discussion of Related Art
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention.
In the drawings:
FIG. 1 is a block diagram of a conventional uradation driving circuit of a liquid crystal display;
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
FIG. 4 is a functional block diagram of a gradation driving circuit consistent with the present invention. Gradation driving circuit 400 typically receives 6 bits designating a particular gray scale voltage output. The upper three bits are supplied to second multiplexer 12 for selecting one of 8 source voltages V.sub.8, V.sub.16, V.sub.24, V.sub.32, V.sub.40, V.sub.48, V.sub.56, and V.sub.64, and the lower three bits are input to first multiplexer 11 for selecting one of source voltages V.sub.0 to V.sub.7. Further, one of output lines 40 is driven high and supplied to scaling part 13. The source voltage selected by the first multiplexer are input to scaling part 13, which scales or multiplies the selected one of source voltages V.sub.0 to V.sub.7 by an appropriate gamma-corrected scaling factor. The output of scaling part 13 along with the source voltage selected by second multiplexer 12 are supplied to a combining circuit, in this case subtraction part 14, which arithmetically combines, by subtraction, the scaled source voltage selected by first multiplexer 11 from the source voltage selected from second multiplexer 12. As a result, a gamma correct gray scale voltage is output to the sub-pixel (or pixel). As discussed in detail below, however, the combining circuit can include an adder circuit instead of a substraction circuit.
FIG. 5 illustrates gradation driving circuit 400 in greater detail. Second multiplexer 12 receives upper input data bits D3-D5, to thereby drive high one of outputs 01 to 08. The selected output is coupled to a level shifter 50, which generates an appropriate potential to turn on a corresponding pass transistor (not shown) to supply the desired one of source voltages V.sub.8 to V.sub.64, Vref2, to scaling part or circuit 13.