Driving circuit for liquid-crystal display device

A driving circuit for a liquid-crystal display device having display elements and n signal lines coupled to the display elements, where n is an integer, said driving circuit comprising:

• a shift register which outputs n control signals that drive the n signal lines, respectively, the shift register having a plurality of cascaded stages, each preceding stage connected by a single output line to a next, successive stage and each of the plurality of cascaded stages corresponding to one of the control signals and including
• delay elements connected in parallel, each of the delay elements having a unit delay time and producing a corresponding output signal;
• and
• selector means for receiving the output signals of the delay elements, for selecting, in response to a select signal, at least one of the output signals of the delay elements and for outputting the at least one of the output signals as the one of the control signals corresponding to the respective stage via the single output line to the next, successive stage of the plurality of cascaded stages;
• and
• defect detecting means for detecting defects which occur in at least one of the delay elements and for generating the select signal in response thereto.

A driving circuit for a liquid-crystal display device having display elements and n signal lines coupled to the display elements, where n is an integer, said driving circuit comprising:

• n primary driving voltage output circuits which produce respective outputs and drive, respectively, the n signal lines;
• n secondary driving voltage output circuits which produce respective outputs and correspond, respectively, to said n primary driving voltage output circuits, each primary driving voltage output circuit and a corresponding secondary driving voltage output circuit defining one of a plurality of cascading stages of the driving circuit, each preceding stage connected by a single output line to a next, successive stage;
• control means for controlling operations of said n primary driving voltage output circuits;
• defect detecting means for detecting defects in said n primary driving voltage output circuits and for generating n select signals in response thereto;
• and
• selector means for selecting, at each stage, either the a respective primary driving voltage output circuit or the corresponding secondary driving voltage output circuit of the respective stage in accordance with the n select signals and for providing the output thereof to the next, successive stage of the cascaded stages except for an output of a last stage of the cascaded stages.

A driving circuit for a liquid-crystal display device having display elements and n signal lines coupled to the display elements, where n is an integer, the driving circuit comprising:

• n primary driving voltage output circuits which respectively correspond to, and respectively drive, the n signal lines;
• at least one secondary driving voltage output circuit, each secondary driving voltage output circuit corresponding to a respective group of m primary driving voltage output circuits, where m is less than n;
• control means for respectively providing m control signals to the m primary driving voltage output circuits within a respective group to thereby control operations of the m primary driving voltage output circuits within the group;
• first switch means for selectively and respectively connecting the n primary driving voltage output circuits to the n signal lines;
• second switch means for selectively providing the m control signals of a respective group to the corresponding secondary driving voltage output circuit;
• third switch means for selectively connecting, for the m primary driving voltage output circuits of each group, the corresponding secondary driving voltage output circuit to a respective signal line of the signal lines corresponding to the primary driving voltage output circuits in the group;
• and
• defect detecting means for detecting defects that occur in the m primary driving voltage output circuits of each group and for controlling the first, second and third switch means so that a signal line corresponding to a primary driving voltage output circuit, of the respective group, in which a defect is detected is driven by the secondary driving voltage output circuit of the respective group.

A driving circuit for a liquid-crystal display device having display elements, including redundant display elements, and n signal lines coupled to the display elements, where n is an integer, said driving circuit comprising:

• n driving voltage output circuits respectively corresponding to and respectively driving the n signal lines upon serial activation at respective, different timings to display data on the liquid-crystal display device;
• defect detecting means for detecting defects in the n driving voltage output circuits, thereby identifying defective driving voltage output circuits;
• and
• control means for controlling the n driving voltage output circuits so that, when a defective driving voltage output circuit is identified by the defect detection means, a non-defective driving voltage output circuit adjacent to the defective driving voltage output circuit, and a corresponding signal line of the non-defective driving voltage output circuit are used to display data which was to be displayed by the defective driving voltage output circuit.

A driving circuit for a liquid-crystal display device having display elements, including redundant display elements, and n signal lines coupled to the display elements, where n is an integer, said driving circuit comprising:

• n driving voltage output circuits respectively corresponding to and respectively driving the n signal lines to display data on the liquid-crystal display device;
• defect detecting means for detecting defects in said n driving voltage output circuits;
• and
• control means for supplying to the n driving voltage output circuits, timing signals to control successive operations of the voltage driving output circuits, so that where i represents an integer less than n, when a defect in an ith driving voltage output circuit is not detected by the defect detecting means, a successive timing signal of the ith driving voltage output circuit is provided as a timing signal for the (i+1)th driving voltage output circuit, and when a defect is detected in the ith driving voltage output circuit by the defect detecting means, a timing signal is provided to the (i+1)th driving voltage output circuit which is the timing signal provided to the ith driving voltage output circuit prior to the successive timing signal of the ith driving voltage output circuit, which was to be used to cause display of the display data by the ith driving voltage output circuit and a corresponding signal line.

A driving circuit for a liquid-crystal display device having display elements and n signal lines coupled to the display elements, where n is an integer, the driving circuit comprising:

• a shift register which outputs n control signals to drive the n signal lines, respectively, the shift register having a plurality of cascaded stages, each stage corresponding to one of the n control signals and comprising:
• first, second and third delay elements connected in parallel, each of the delay elements having a unit delay time and producing a corresponding output signal,
• a mismatch determining means, receiving the corresponding output signals of the first and second delay elements, for generating a mismatch signal by performing an XOR operation of the received output signals, and
• selection means, receiving the mismatch signal from the mismatch determining means and the outputs of the first and third delay elements, for outputting one of the output signals of the first and third delay elements based on the mismatch signal, the signal output by the selection means being the n control signal corresponding to the respective stage.

A driving circuit for a liquid-crystal display device having display elements and n signal lines coupled to the display elements, where n is an integer, the driving circuit comprising:

• a shift register which outputs n control signals to drive the n signal lines, respectively, the shift register having a plurality of cascaded stages, each stage corresponding to one of the n control signals and comprising:
• first, second and third delay elements connected in parallel, each of the delay elements having a unit delay time and producing a corresponding output signal,
• first, second and third capacitances corresponding to, and respectively connected to, the corresponding outputs of the first, second and third delay elements, each thereof latching the voltage of the corresponding output;
• and
• an average value determining means, receiving the voltages latched by the capacitances, for generating a corresponding output signal based on the average value of the voltages across the capacitances, the output signal of the average value determining means being the n control signal corresponding to the respective stage.