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US 5,859,608 AGranted
Successive approximation and shift register without redundancy
AssigneeSGS-Thomson Microelectronics S.A.
InventorsGiona Fucili, Lorenzo Papillo, Andrea Pasquino, Annamaria Rossi, Alberto Gola
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Abstract
A successive approximation shift register without redundancy for a finite-state machine of the sequential type, is also effective to store the machine states. The shift register comprises a chain of logic circuits of the bistable type (FF0,FF1, . . . ) having an input stage with selectable signal inputs which are feedback connected through logic OR gate circuits (OR0,OR1, . . . ,OR6).
Claims4
A successive-approximation N-bit, analog-to-digital converter, comprising:
- a digital-to-analog converter, having an N-bit digital input and an analog output which depends on data received at said digital input;
- a comparator, connected to receive an external analog signal and also said analog output from said digital-to-analog converter, and to generate an output signal therefrom;
- and
- N bistable circuits, each having a multiplexing circuit, and a single corresponding flip-flop, and each connected to provide one bit of output to a respective one of said digital inputs of said converter, and each connected to receive said output signal from said comparator, and including a logic gate connected between the multiplexing circuit and the single, corresponding flip-flop to enable synchronous operation with a reset signal;
- wherein said bistable circuits are mutually interconnected to implement a finite state machine function which forces said N-bit digital input of said digital-to-analog converter toward an N-bit value which corresponds to analog-to-digital conversion of said external analog value.
2 more elements
Dependencies are inferred from the claim text.