Frequency trimmable oscillator and frequency multiplier

A MOS implementable oscillator circuit, operable from a voltage source Vdd, that receives an input clock signal OSCIN, and provides an output clock signal OSCOUT wherein frequency of OSCOUT is the product of K times frequency of OSCIN, where K is an integer or a non-integer, the circuit comprising:

• a current generator providing a core reference current Iosc0 and further providing a mirrored first trim current Iosc1.apprxeq.(M/N).times.Iosc0, where M and N are each integers, wherein Iosc0 and Iosc1 are each substantially independent of changes in said Vdd;
• a delay unit coupled to receive said input clock signal OSCIN and coupled to said current generator, said delay unit including first and second strings of series-coupled MOS devices in which a MOS device is coupled as a diode, wherein when conducting, current through each diode-coupled MOS device is a current Iosc3 mirroring said core reference current Iosc0, said delay unit further outputting first and second non-overlapping enabling signals coupled respectively to said first and second strings of series-coupled MOS devices;
• a first capacitor C1 coupled to receive current from the first string of series-coupled MOS devices, wherein during current flow, a ramp-like voltage signal appears across C1;
• a second capacitor C2 coupled to receive current from the second string of series-coupled MOS devices, wherein during current flow, a ramp-like voltage signal appears across C2 such that when C2 is charged with current C1 is discharged and vice versa;
• a multiplexer unit, coupled to receive said input clock signal OSCIN, coupled to receive said ramp-like voltage across C1, coupled to receive said ramp-like voltage across C2, and coupled to receive said first and second non-overlapping enabling signals;
• a programmable tracking delay unit, coupled to said current generator and including third and fourth strings of series-coupled MOS devices in which a MOS device is coupled as a diode, wherein when conducting, current through each diode-coupled MOS device mirrors said core reference current Iosc0;
• a first programmable capacitance C1p coupled to said third string of series-coupled MOS devices so as to create a ramp-like voltage signal across said C1p, C1p having a capacitance magnitude that is programmably selectable;
• a second programmable capacitance C2p coupled to said fourth string of series-coupled MOS devices so as to create a ramp-like voltage signal across said C2p, C2p having a capacitance magnitude that is programmably selectable;
• a comparator unit coupled to receive and compare a threshold voltage Vt reference generated by said multiplexer unit with each said ramp-like voltage signal appearing across C1p and C2p, and to output at least first and second comparator output signals;
• set-reset logic coupled to receive said first and second comparator output signals and to output said output clock signal OSCOUT;
• wherein said programmable tracking delay unit includes a programmable small delay unit, coupled to receive said output clock signal OSCOUT and a complement thereof, and to provide third and fourth enabling signals coupled respectively to said third and fourth string of series-coupled MOS devices;
• and
• wherein a ratio of frequency of OSCOUT/frequency of OSCIN is given by a ratio (C4+C2)/(C1p+C2p).

A method for providing a MOS implementable frequency oscillator operable from a voltage source Vdd and having an output frequency substantially independent of Vdd, the method comprising the following steps:

• (a) generating a core reference current Iosc0 and a mirrored first trim current Iosc1.apprxeq.(M/N).times.Iosc0, where M and N are each integers, wherein Iosc0 and Iosc1 are each substantially independent of changes in Vdd;
• (b) providing a programmable delay unit including first and second value-programmable capacitors Cp1, Cp2 coupled to said current generator to receive mirrored currents A.times.(M/N).times.Iosc0 wherein A is a constant proportional to a W/L ratio for a MOS device generating said Iosc1, so as to generate first and second ramp-like voltage signals across said capacitors Cp1 and Cp2 having a voltage slewrate proportional to A.times.(M/N).times.Iosc0/capacitance, where capacitance is Cp1 or Cp2;
• (c) providing a comparator unit, coupled to receive said first and second ramp-like voltage signals with a reference voltage proportional to nominal threshold voltage for a MOS device in said current generator, and outputting at least first and second comparator output signals;
• (d) providing logic coupled to receive said first and second comparator output signals and to output an OSCOUT signal of said frequency oscillator;
• wherein said OSCOUT signal is fedback to said programmable delay unit to toggle said A.times.(M/N).times.Iosc0 current flow on and off to said capacitors Cp1 and Cp2 such that said ramp-like voltage signals are generated alternately across said capacitors Cp1 and Cp2 with a period of oscillation of said OSCOUT signal;
• wherein said OSCOUT signal has a frequency that is substantially independent of Vdd, and wherein selecting at least one of an integer M and a value of A permits trimming said frequency to compensate for process variations in fabricating said oscillator circuit.