Frequency synthesizer using divided and frequency converted DDS signal as reference for PLL
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKenji Itoh, Ken'ichi Tajima, Shuji Nishimura, Akio Iida
Life of this patent
Estimating the term…
Loading patent…
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKenji Itoh, Ken'ichi Tajima, Shuji Nishimura, Akio Iida
Estimating the term…
A frequency synthesizer having reduced spurious components for use in a receiving and transmitting apparatus. The frequency synthesizer includes a direct digital synthesizer (DDS) for generating a first signal having a first frequency determined by channel setting data. The first signal is applied to a frequency divider to generate a divided signal having a divided frequency. The divided signal is applied to a frequency converter for shifting the divided frequency by a shift frequency interval to provide a reference signal having a reference frequency. The reference signal is applied to a phase locked loop (PLL) for generating a final signal having a predetermined frequency characteristic.
A frequency synthesizer for generating a signal of desired frequency, comprising:
A method for synthesizing a final signal having a predetermined frequency comprising steps of:
A frequency synthesizer for generating a final signal having a predetermined frequency characteristic, the frequency synthesizer comprising:
A method for synthesizing a final signal having a predetermined frequency characteristic, the method comprising the steps of:
A frequency synthesizer for generating a final signal having a predetermined frequency characteristic, the frequency synthesizer comprising:
Dependencies are inferred from the claim text.