Variable delay circuit

A variable delay circuit that delays an input signal for a desired time and outputs a delay signal comprising:

• N (N is an integer and at least 2) load transistors, N control transistors for controlling respective load transistors, and N current limiting means, each of the load and control transistors having an input electrode, an output electrode, and a control electrode, the control and output electrodes of each of the load transistors being connected together, respective load transistors, current limiting means, and control transistors being connected in series, the current limiting means being connected between the output electrode of the control transistor and the input electrode of the load transistor, as N load transistor pairs, the N load transistor pairs being connected in parallel to form a load transistor group;
• and
• a switching transistor turned on and off in response to a signal input to a gate of the switching transistor, the load transistor group and the switching transistor being connected in series at the control electrodes of the load transistors and an input electrode of the switching transistor, between first and second power supplies wherein the signal input is delayed in response to control signals respectively input to the control electrodes of the N control transistors, and the delayed signal input is output from a connection node of the load transistor group and the input electrode of the switching transistor.

A variable delay circuit that delays an input signal for a desired time and outputs a delay signal comprising:

• N (N is an integer and at least 2) load transistors, N control transistors for controlling respective load transistors, and N current limiting means, each of the load and control transistors having an input electrode, an output electrode, and a control electrode, the control and output electrodes of each of the load transistors being connected together, respective load transistors, current limiting means, and control transistors being connected in series, the current limiting means being connected between the output electrode of the control transistor and the input electrode of the load transistor, as N load transistor pairs, the N load transistor pairs being connected in parallel to form a load transistor group, the load transistors in the N load transistor pairs having respective sizes and the sizes varying in a binary sequence;
• and
• a switching transistor turned on and off in response to a signal input to a gate of the switching transistor, the load transistor group and the switching transistor being connected in series at the control electrodes of the load transistors and an input electrode of the switching transistor, between first and second power supplies wherein the signal input is delayed in response to control signals respectively input to the control electrodes of the N control transistors, and the delayed signal input is output from a connection node of the load transistor group and the input electrode of the switching transistor.