System and method for a glitchless transition between differing delay paths

A method of providing a system for switching between delay pathes differing magnitudes without generating any glitches and false edges comprising the steps of:

• providing no delay circuit means for outputting a signal having no delay, with respect to an input signal;
• providing delay output circuit means for outputting a delayed form of said input signal;
• providing multiplexer means having a first input coupled to said output of said no delay circuit means and a second input coupled to said output of said delay output circuit means for outputting one of said signal having no delay or said delayed form of said input siqnal;
• providing control means coupled to said multiplexer means for signaling said multiplexer means to output one of said signal having no delay or said delayed form of said input signal and for controlling the switching of said output of said multiplexer means so that when said output of said multiplexer means switches from said signal having no delay to said delayed form of said input signal and when said output of said multiplexer means switches from said delayed form of said input signal to said signal having no delay, no glitches and false edges are generated;
• providing delay circuit means having an input coupled to said input signal and all output coupled to said delay output circuit means for generating said delayed form of said input signal;
• and
• providing enable signal means coupled to said delay circuit means for controlling when said delay circuit means is active and inactive and further coupled to said control means for signalling said control means to switch said output of said multiplexer means from said signal having no delay to said delayed form of said input signal and from said delayed form of said input signal to said signal having no delay so that no glitches and false edges are generated and outputted by said multiplexer means;
• wherein said step of providing no delay circuit means further comprises the steps of:
• providing no delay circuit latchmeans for outputting said signal having no delay;
• and
• providing no delay circuit logic gate means having a first input coupled to said input signal, a second input coupled to said control means, a third input coupled to said enable signal means, and an output coupled to said no delay circuit latch means for generating a signal to control said output of said no delay circuit latch means.

A system for switching between delay paths of differing magnitudes without generating any glitches and false edges comprising, in combination:

• no delay circuit means for outputting a signal having no delay, with respect to an input signal, said no delay circuit means comprising:
• no delay circuit latch means for outputting said signal, having no delay;
• and
• no delay circuit logic gate means having a first input coupled to said input signal, a second input coupled to a control means, a third input coupled to an enable signal means, and an output coupled to said no delay circuit latch means for generating a signal to control said no delay circuit latch means;
• delay output circuit means for outputting a delayed form of said input signal, said delay output circuit means comprising:
• delay output circuit latch means for outputting said delayed form of said input signal;
• and
• delay output circuit logic gate means having a first input coupled to a delay circuit means, a second input coupled to said enable signal means, and an output coupled to said delay output circuit latch means for generating a signal to control said delay output circuit latch means;
• multiplexer means having a first input coupled to said no delay circuit means, a second input coupled to said delay output circuit means, and a third input coupled to said control means for outputting one of said signal having no delay or said delayed form of said input signal;
• said control means coupled to said multiplexer means for signalling said multiplexer means Lo output one of said signal haviriq no delay and said delayed form of said input signal and for controlling the switching of said output of said multiplexer mean so that when said output of said multiplexer means switches from said signal having no delay to said delayed form of said input signal and when said output of said multiplexer means switches from said delayed form ot said input signal to said signal having no delay, no glitches and false edges are generated, said control means comprising:
• control latch means having an input coupled to said enable signal means and outputs coupled to said multiplexer means for signalling said muitiplexer means to output one of said signal having no delay outputted from said no delay circuit means or said delayed form of said input signal outputted from said delay output circuit means;
• and
• control logic gate means having a first input coupled to said enable signal means, a second input coupled to said delay output circuit means, and an output coupled to said control latch means for sending a signal to said control latch means to signal said multiplexer to output said delayed form of said input signal outputted from said delay output circuit means;
• said delay circuit means having an input coupled to said input signal and an output coupled to said delay output circuit means for generating said delayed form of said input signal;
• and
• said enable signal means coupled to said delay circuit means and to said control means for controlling when said delay circuit means is active and inactive and for signalling said control means to switch said output of said multiplexer means from said signal having no delay to said delayed form of said input signal and from said delayed form of said input signal to said signal having no delay so that no glitches and false edges are generated and outputted by said multiplexer means.