Programmable slew rate control circuit for output buffer

A slew rate control circuit for an output circuit of an integrated circuit including:

• an input node for receiving an input signal;
• an output node for providing an output signal;
• a plurality of cascaded delay circuits, each delay circuit having an input and an output, each delay circuit having a time delay selected so as to provide a predetermined amount of delay from the input to the output thereof, the input of a first one of said delay circuits coupled to said input node forming an undelayed control node, the outputs of said cascaded delay circuits forming successively delayed control nodes;
• a plurality of pulldown stages, each stage having at most one pulldown transistor, each pulldown tansistor having a control terminal and first and second main terminals, the first main terminal of each pulldown transistor coupled to a voltage rail, the second main terminal of each pulldown transistor coupled to said output node;
• a programmable switching circuit comprising a plurality of switches connected between the control terminals of ones of said pulldown transistors and the undelayed control node and the successively delayed control nodes;
• and
• a control circuit, responsive to programming information, configured to selectively connect the control terminal of each of said pulldown transistors to either the undelayed control node, any one of the successively delayed control nodes, or said voltage rail.

A slew rate control circuit for an output circuit of an integrated circuit including:

• an input node for receiving an input signal;
• an output node for providing an output signal;
• a first control circuit stage including 1 to n first control sub-stages, each first control sub-stage having at most one first control sub-stage transistor, each first control sub-stage transistor having a control terminal and first and second main terminals, the control terminals of each first control sub-stage transistor coupled to said input node, the first main terminal of each first control sub-stage transistor coupled to a voltage rail, the second main terminal of each first control sub-stage transistor coupled to said output node;
• at least one subsequent control circuit stage each including 1 to n subsequent control sub-stages, each subsequent control sub-stage having at most one subsequent control sub-stage transistor, each subsequent control sub-stage transistor having a control terminal and first and second main terminals, the first main terminal of each subsequent control sub-stage transistor in each subsequent control circuit stage coupled to said voltage rail, the second main terminal of each subsequent control sub-stage transistor in each subsequent control circuit stage coupled to said output node;
• and
• a delay circuit associated with each subsequent control circuit stage and coupled to said input node, each delay circuit coupled to the control terminals of all subsequent control sub-stage transistors the subsequent control stage with which it is associated, each delay circuit comprises a pair of cascaded inverters, each of said inverters sized so as to provide a predetermined amount of delay therethrough.

A programmable slew rate control circuit for an output circuit of an integrated circuit including:

• an input node for receiving an input signal;
• an output node for providing an output signal;
• a plurality of control stages, each control stage having at most one control stage transistor, each control stage transistor having a control terminal and first and second main terminals, the first main terminal of each control stage transistor coupled to a voltage rail, the second main terminal of each control stage transistor coupled to said output node;
• a plurality of cascaded inverters each having an input and an output, a first one of said inverters having its input connected to said input node, each of said inverters sized so as to provide a predetermined amount of delay therethrough, said plurality of cascaded inverters forming a plurality of successively delayed control nodes at inputs and outputs thereof;
• a plurality of pass gates, each of said pass gates connected between the control terminals of a selected one of said control stage transistors and a selected one of said successively delayed control nodes;
• and
• means for selectively activating ones of said plurality of pass gates to connect the control terminal of each one of said control stage transistors to a selected one of said successively delayed control nodes.

A slew rate control circuit for an output circuit of an integrated circuit including:

• an input node for receiving an input signal;
• an output node for providing an output signal;
• a first control circuit stage including three first control sub-stages, each control sub-stage including at most one first control sub-stage transistor, each first control sub-stage transistor having a control terminal and first and second main terminals, the control terminals of each first control sub-stage transistor coupled to said input node, the first main terminal of each first control sub-stage transistor coupled to a voltage rail, the second main terminal of each first control sub-stage transistor coupled to said output node;
• a second control circuit stage including two second control sub-stages, each second control sub-stage including at most one second control sub-stage transistor, each second contol sub-stage transistor having a control terminal and first and second main terminals, the control terminals of each second control sub-stage transistor coupled to a first delayed control node, the first main terminal of each second control sub-stage tansistor coupled to said voltage rail, the second main terminal of each second control sub-stage transistor coupled to said output node;
• a third control circuit stage including a third control sub-stage including at most one third control sub-stage transistor having a control terminal and first and second main terminals, the control terminal of said third control sub-stage tmansistor coupled to a second delayed control node, the first main terminal of said third control sub-stage transistor coupled to said voltage rail, the second main terminal of said third control sub-stage transistor coupled to said output node;
• a fourth control circuit stage including a fourth control sub-stage including at most one fourth control sub-stage having a control terminal and first and second main terminals, the control terminal of said fourth control sub-stage transistor coupled to a third delayed control node, the first main terminal of said fourth control sub-stage transistor coupled to said voltage rail, the second main terminal of said fourth control sub-stage transistor coupled to said output node;
• a fifth control circut stage including a fifth control sub-stage including at most one fifth control sub-stage transistor having a control terminal and first and second main terminals, the control terminal of said fifth control sub-stage transistor coupled to a fourth delayed control node, the first main terminal of said fifth control sub-stage transistor coupled to said voltage rail, the second main terminal of said fifth control sub-stage transistor coupled to said output node;
• a sixth control circuit stage including a sixth control sub-stage including at most one sixth control sub-stage transistor having a control terminal and first and second main terminals, the control terminal of said sixth control sub-stage transistor coupled to a fifth delayed control node, the first main terminal of said sixth control sub-stage tansistor coupled to said voltage rail, the second main terminal of said sixth control sub-stage transistor coupled to said output node;
• a first pair of cascaded inverters connected between said input node and said first delayed control node;
• a second pair of cascaded inverters connected between said first delayed control node and said second delayed control node;
• a third pair of cascaded inverters connected between said second delayed control node and said third delayed control node;
• a fourth pair of cascaded inverters connected between said third delayed control node and said fourth delayed control node;
• and
• a fifth pair of cascaded inverters connected between said fourth delayed control node and said fifth delayed control node;
• wherein each inverter in said first through fifth pairs of cascaded inverters is sized so as to provide a predetermined amount of delay therethrough.

A slew rate control circuit for an output circuit of an integrated circuit including:

• input means for receiving an input signal;
• output means for providing an output signal;
• a plurality of switch means for making a connection between a voltage rail and said output means;
• a first delay means connected to said input node for generating a first delayed input signal;
• a second delay means connected to said input node for generating a second delayed input signal;
• a third delay means connected to said input node for generating a third delayed input signal;
• a fourth delay means connected to said input node for generating a fourth delayed input signal;
• a fifth delay means connected to said input node for generating a fifth delayed input signal;
• a first control means, responsive to said input means, for activating three of said switch means in response to said input signal;
• a second control means, responsive to said first delayed input signal means, for activating two of said switch means;
• a third control means, responsive to said second delayed input signal, for activating one of said switch means;
• a fourth control means, responsive to said third delayed input signal, for activating one of said switch means;
• a fifth control means, responsive to said fourth delayed input signal, for activating one of said switch means;
• a sixth control means, responsive to said fifth delayed input signal, for activating one of said switch means.