Digital audio frame and block synchonization

Abstract

A digital audio frame and block synchronization signal is generated from a reference clock having a nominal 50% duty cycle except that one out of every N cycles has a different duty cycle, where N corresponds to a block span of ancillary data within the frame samples of the digital audio. A phase locked loop includes a loop counter that provides a sample clock synchronized with the reference clock. A block counter subdivides the sample clock by N to produce a block clock. A logic circuit has the reference clock and a current count from the loop counter as inputs, and detects when the Nth non-50% duty cycle occurs to generate a reset signal. The reset signal is used to reset the block counter so that the block clock is synchronized with the reference clock.

Dependencies are inferred from the claim text.