Dynamic logic circuit

A dynamic logic circuit, comprising:

• a precharge transistor including a gate terminal and a source-to-drain path coupled between a first-supply-voltage node and a precharge node;
• a logic block including at least one transistor coupled between a second-supply-voltage node and a logic-block output node, said at least one transistor in the logic block further including a gate terminal couplable to an input signal;
• an evaluation transistor having a source-to-drain path and a gate terminal, the source-to-drain path coupled between the logic-block output node and the precharge node, the gate terminal coupled to a clock signal node;
• and
• a delay coupled between the clock signal node and the gate terminal of the precharge transistor.

A dynamic logic circuit, comprising:

• a dynamic logic block having a plurality of input transistors, the arrangement of the input transistors determining the logic function of the circuit;
• a precharge transistor for precharging an output of the dynamic logic circuit to a first voltage level during a precharge phase;
• an evaluation transistor between the dynamic logic block and the precharge transistor for allowing charge sharing between the output of the dynamic logic circuit and the dynamic logic block;
• and
• the precharge and evaluation transistors are activated simultaneously for a period of time.

A dynamic logic circuit, comprising:

• a dynamic logic block having input transistors all coupled in parallel;
• a precharge transistor;
• an evaluation transistor between the dynamic logic block and the precharge transistor;
• a clock signal node directly connected to the evaluation transistor for switching the evaluation transistor between active and inactive states;
• and
• a delay coupled to the precharge transistor for delaying the clock signal to the precharge transistor with respect to the evaluation transistor.