Circuit and method for signal processing
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorHiroyuki Yamauchi
Life of this patent
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Abstract
An exclusive OR circuit is provided which detects whether or not a preceding-stage logical output value and a subsequent-stage logical output value agree. When these logical output values are found to agree, a NAND circuit functions to cut off the supply of a clock signal to a first and second switch circuits and to a latch circuit. Accordingly, when there occur no data changes between clock signal cycles, in a switch circuit and a latch circuit both arranged between each stage of a pipeline, the charge/discharge of the capacitance of gate electrodes of transistors forming these circuits is prevented, thereby reducing power consumption.
Claims14
A signal processing circuit comprising a switch circuit for allowing or cutting off the transfer of a logical output and a circuit capable of latching said logical output,
- said signal processing circuit further comprising:
- control means for controlling said switch circuit and said latch circuit according to the AND of a clock signal and a comparison result signal indicative of a result obtained by making a comparison between a previous logical output value and a current logical output value.
A signal processing method for use in a circuit comprising a switch circuit for allowing or cutting off the transfer of a logical output and a circuit capable of latching a logical output, said signal processing method comprising the steps of:
- making a comparison between a previous logical output value and a current logical output value;
- supplying a clock signal to said switch circuit and to said latch circuit when said logical output values disagree;
- cutting off the supply of said clock signal to said switch circuit and to said latch circuit when said logical output values agree.
Dependencies are inferred from the claim text.