High-voltage isolated high output impedance NMOS

Abstract

A semiconductor transistor device includes a first doped region 34 of a first conductivity type; a second doped region 30 of the first conductivity type formed at the surface of the first doped region 34, the second doped region 30 has a higher doping concentration than the first doped region 34; a source region 24 of a second conductivity type formed at the surface of the second doped region 30; a lightly doped drain region 28 of the second conductivity type surrounding the first doped region 34, the lightly doped drain region 28 has a lower doping concentration than the source region 24, the lightly doped drain region 28 is spaced apart from the second doped region 30; a buried layer 40 of the second conductivity type below the first doped region 34 and coupled to the lightly doped drain region 28; and a gate 32 overlying and spaced apart from the first doped region 34 and the second doped region 30.

Dependencies are inferred from the claim text.