Methods for gap fill and planarization of intermetal dielectrics

A method of manufacturing an integrated circuit device comprising:

• providing semiconductor device structures in and on a semiconductor substrate;
• covering said semiconductor device structures with an insulating layer and planarizing said insulating layer;
• depositing a conducting layer overlying said insulating layer;
• depositing a hard mask overlying said conducting layer wherein said hard mask comprises one of the group containing silicon nitride, silicon oxynitride, and boron nitride and wherein said hard mask acts as an anti-reflective coating;
• patterning said conducting layer and said hard mask to form conducting lines wherein a gap is formed between said conducting lines;
• depositing a first dielectric layer over the surfaces of said conducting lines wherein said gap remains between said conducting lines;
• depositing a second dielectric layer overlying said first dielectric layer wherein said gap is filled by said second dielectric layer;
• planarizing said first and second dielectric layers wherein said hard mask acts as an etch stop;
• depositing a third dielectric layer over said planarized first and second dielectric layers;
• etching via openings through said third dielectric layer and said hard mask to said conducting lines;
• and
• filling said via openings with a second conducting layer to complete electrical connections in the fabrication of said integrated circuit device.