Method of forming contact plugs

A method for preparing an integrated circuit structure, said structure having a silicon substrate with a plurality of gate stacks and associated contact regions formed thereon, each of said gate stacks having a bottom at said substrate, a top above said substrate, sides extending upward from said bottom to said top, and top comers at the convergence of said top and said sides, each of said gate stacks being enclosed in a silicon nitride enclosure layer, said method comprising:

• producing a BPSG planarization layer over said substrate and all structures thereon;
• selectively removing said BPSG planarization layer over at least one of said contact regions and etching said silicon nitride enclosure layer to form facets thereon at the top comers of said gate stacks;
• depositing a layer of doped polysilicon to contact at least one of said contact regions;
• and
• removing all material deposited over the substrate from the top down to a depth at least as low as a top of said dielectric planarization layer.

A method for preparing an integrated circuit structure, said structure having a substrate with a plurality of gate stacks and associated contact regions formed thereon, each of said gate stacks being enclosed in a dielectric enclosure layer, said dielectric enclosure layer having a bottom at said substrate, a top above said substrate, sides extending upward from said bottom to said top, and a shoulder region at the convergence of said top and said sides, said method comprising:

• etching said shoulder region to form a facet;
• producing a dielectric planarization layer over said substrate;
• providing a patterned photoresist layer upon said dielectric planarization layer;
• isotropically etching said dielectric planarization layer to remove said dielectric planarization layer and expose said contact regions, wherein a stack of said dielectric planarization layer extends from the top of each said dielectric enclosure layer;
• depositing a layer of conducting material to contact said contact regions and said facet;
• and
• removing material deposited over the substrate to isolate the conducting material above the substrate between each said stack of said dielectric planarization layer extending from the top of said dielectric enclosure layer.

A method for preparing an integrated circuit structure, said structure having a substrate with a plurality of gate stacks and associated contact regions formed thereon, each of said gate stacks being enclosed in a dielectric enclosure layer, said dielectric enclosure layer having a bottom at said substrate, a top above said substrate, sides extending upward from said bottom to said top, and a shoulder region at the convergence of said top and said sides, said method comprising:

• producing a dielectric planarization layer over said substrate;
• providing a patterned photoresist layer upon said dielectric planarization layer;
• etching said dielectric planarization layer to remove said dielectric planarization layer over at least one shoulder region of the dielectric enclosure layer enclosing the gate stacks, and to expose at least one of said contact regions;
• etching at least one shoulder region of the dielectric enclosure layer enclosing the gate stacks to form a facet at the shoulder region of the dielectric enclosure layer;
• depositing a layer of conducting material to contact said at least one of said contact regions and to contact the facet at the shoulder region of the dielectric enclosure layer;
• and
• removing material over the substrate to a depth at least as low as the facet at the shoulder region of the dielectric enclosure layer.

A method for preparing an integrated circuit structure, said structure having a substrate with a plurality of gate stacks and associated contact regions formed thereon, each of said gate stacks having a bottom at said substrate, a top above said substrate, sides extending upward from said bottom to said top, and top corners at the convergence of said top and said sides, each of said gate stacks being enclosed in a dielectric enclosure layer, said dielectric enclosure layer having a shoulder region at each of said top corners of said gate stacks, said method comprising:

• producing a dielectric planarization layer over said substrate and all structures thereon;
• removing for a first time all materials deposited over the substrate from the top down at least to the top of said dielectric enclosure layer enclosing the gate stacks, leaving a planar surface;
• providing a patterned photoresist layer on said planar surface;
• anisotropically etching said dielectric planarization layer to remove said dielectric planarization layer at areas left exposed by the patterned photoresist layer including an area over at least one of said contact regions;
• isotropically etching said patterned photoresist layer to enlarge the areas left exposed by said patterned photoresist layer;
• anisotropically etching a step in at least one shoulder region of the dielectric enclosure layer enclosing the gate stacks;
• depositing a layer of conducting material to contact at least one of said contact regions;
• and
• removing for a second time all material deposited over the substrate from the top down to a depth at least as low as the top of the dielectric enclosure layer enclosing the gate stacks.

A method for preparing an integrated circuit structure, said structure having a substrate with a plurality of gate stacks and associated contact regions formed thereon, each of said gate stacks having an electrically conductive gate electrode with a width, said method comprising:

• forming a dielectric enclosure layer so as to enclose each said gate stack, each said dielectric enclosure layer having:
• a bottom at said substrate;
• a top above said substrate and a facet between said top and bottom;
• a width at the top that is less than or equal to the width of the electrically conductive gate electrode;
• and
• a width at the bottom that is greater then the width of the electrically conductive gate electrode;
• forming a dielectric planarization layer upon said contact regions and said dielectric enclosure layers;
• selectively removing said dielectric planarization layer to expose said contact regions;
• forming a layer of conducting material to contact said contact regions;
• and
• forming contact plugs from the layer of conducting material, each contact plug being in contact with one of said contact regions and said facet and being isolated one from another by two of the dielectric enclosure layers.

A method for forming an integrated circuit structure, said structure having a substrate with a plurality of gate stacks and associated contact regions formed thereon, each of said gate stacks having an electrically conductive gate electrode, said method comprising:

• forming a dielectric enclosure layer so as to enclose each said gate stack, each said dielectric enclosure layer having a bottom at said substrate, a top above said substrate, sides extending upward from said bottom to said top, and a shoulder region at the convergence of said top and said sides, wherein said contact regions are exposed;
• selectively removing the dielectric enclosure layers to form facets at the shoulder regions thereon;
• forming a dielectric planarization layer over said exposed contact regions and said dielectric enclosure layers;
• selectively removing said dielectric planarization layer to expose said contact regions;
• forming a layer of conducting material to contact said contact regions and to contact the facets at the shoulder region of the dielectric enclosure layer;
• and
• forming contact plugs from the layer of conducting material, each contact plug being in contact with one of said contact regions and being isolated one from another by two of the dielectric enclosure layers.

A method for preparing an integrated circuit structure, said structure having a substrate with a plurality of gate stacks and associated contact regions formed thereon, each of said gate stacks having an electrically conductive gate electrode with a width, said method comprising:

• forming a dielectric enclosure layer so as to enclose each said gate stack, each said dielectric enclosure layer having:
• a bottom at said substrate;
• a top above said substrate;
• sides extending upward from said bottom to said top;
• a shoulder region at the convergence of said top and said sides;
• a width at the top that is less than or equal to the width of the electrically conductive gate electrode;
• and
• a width at the bottom that is greater then the width of the electrically conductive gate electrode;
• selectively removing the dielectric enclosure layers to form facets at the shoulder regions thereon;
• forming a dielectric planarization layer upon said contact regions and said dielectric enclosure layers;
• selectively removing said dielectric planarization layer to expose said contact regions;
• forming a layer of conducting material to contact said contact regions and to contact the facets at the shoulder region of the dielectric enclosure layer;
• and
• forming contact plugs from the layer of conducting material, each contact plug being in contact with one of said contact regions and being isolated one from another by two of the dielectric enclosure layers.