Electrically conductive substrate interconnect continuity region and method of forming same with an angled implant

A method for forming a conductive interconnect in a substrate, comprising the following steps:

• forming a control layer overlying the substrate;
• implanting ions in the substrate under the control layer to form the conductive interconnect, the ions having a trajectory substantially oblique to a face surface of the substrate;
• forming a buried contact region of the substrate adjacent to and in electrical contact with the conductive interconnect;
• forming a gate of a transistor from the control layer;
• forming a terminal of the transistor adjacent and in electrical contact with the conductive interconnect.

A method for forming a conductive interconnect in a substrate, comprising the following steps:

• forming a control layer overlying the substrate;
• implanting ions having a trajectory substantially oblique to a face surface of the substrate to form the conductive interconnect under the control layer;
• forming a buried contact region of the substrate adjacent to the conductive interconnect;
• forming a transistor gate from the control layer;
• and
• forming a transistor terminal of the transistor adjacent to the conductive interconnect, said conductive interconnect interposed between and in electrical communication with said buried contact region and said transistor terminal such that a conductive path is formed from the buried contact region to the transistor terminal through the conductive interconnect.

A method for forming doped regions in a semiconductor substrate, comprising the following steps:

• forming a control layer overlying the substrate;
• implanting ions having a trajectory substantially oblique to a face surface of the substrate to form an electrically conductive interconnect region in the substrate under the control layer;
• diffusing dopants into the substrate to form a buried contact region in the substrate adjacent said conducive interconnect region;
• forming a transistor gate from the control layer;
• and
• implanting ions into the substrate to form a source/drain transistor terminal of the transistor in said substrate adjacent to said conductive interconnect region, wherein said conductive interconnect region is interposed between said buried contact region and said source/drain transistor terminal to form an electrical current path therebetween.

A method for forming electrically conductive first, second, and third regions in a substrate, comprising the following steps:

• forming a control layer over the substrate;
• implanting ions having a trajectory at an angle which is substantially oblique to a face surface of the substrate to form the electrically conductive first region in a first region in a first area of the substrate under the control layer;
• forming a doped layer overlying a second area of the substrate reserved for a buried contact region;
• driving ions from said doped layer into the second area of the substrate to form the electrically conductive second region;
• forming a transistor gate from the control layer;
• and
• implanting ions to form the electrically conductive third area of the substrate reserved for a source/drain transistor terminal of the transistor, said first region interposed between and adjacent to said second and third regions, the first electrically conductive region forming a current path between the buried contact region and the electricallly conductive third region.

A method for forming electrically conductive regions in a substrate, comprising the steps of:

• forming a patterned control layer overlying the substrate;
• implanting ions into the substrate underlying at least at least a portion of the control layer to form an electrically conductive substrate interconnect region, an angle formed between a face surface of the substrate and a trajectory of said ions being substantially oblique;
• forming a doped layer overlying a second region of the substrate without said control layer;
• driving dopants from said doped layer into said second region of the substrate to form a buried contact region of the substrate in electrical communication with said interconnect region;
• and
• forming a transistor gate from the control layer;
• implanting ions into a third region of the substrate adjacent to said first region to form a transistor terminal of the transistor, wherein the transistor terminal is in electrical communication with said interconnect region such that the interconnect region forms a current path between the buried contact region and the transistor terminal.