Low temperature method of forming gate electrode and gate dielectric

A method of forming an integrated circuit device transistor structure, comprising the steps of:

• providing a substrate;
• forming a mask material on said substrate;
• patterning said mask material to form a mask having substantially vertical and continuous sidewalls;
• forming a doped region within said substrate in alignment with said mask;
• forming a planarization material over said mask;
• planarizing said planarization material such that the top surface of said planarization material is at substantially the same level as the top surface of said mask;
• selectively removing said mask so as to create an opening in said planarization material;
• forming within said opening a gate dielectric;
• and
• forming a gate electrode on said gate dielectric.

A method of forming an integrated circuit device transistor structure, comprising the steps of:

• providing a substrate;
• forming a mask material on said substrate;
• patterning said mask material to form a mask;
• forming a first doped region within said substrate in alignment with said mask;
• forming a spacer adjacent said mask of a material that is different from the mask material, said spacer being formed after patterning said mask material;
• forming a second doped region within said substrate adjacent to said spacer;
• forming a planarization material over said mask and spacer;
• planarizing said planarization material so that the top surface of said planarization material is substantially level with the top surface of said mask;
• selectively removing said mask so as to create a clean opening in said spacer and planarization material, said opening having a substantially similar shape as said mask;
• forming within said opening a gate dielectric;
• and
• forming a gate electrode on said gate dielectric.

A method of forming an integrated circuit device transistor structure on a substrate, comprising the steps of:

• forming a mask in accordance with the dimensions of a to-be-formed gate stack;
• forming a first doped region in the substrate in alignment with the mask;
• depositing a spacer material over the mask;
• forming a spacer structure adjacent the mask by etching said spacer material;
• forming a second doped region in alignment with the spacer structure;
• removing the mask after formation of the doped regions so as to create an opening;
• and
• forming a gate stack within the opening.

A method of forming an integrated circuit device transistor on a substrate, comprising the steps of:

• forming a mask directly on the substrate, said mask having substantially vertical and continuous sidewalls;
• forming a doped region in the substrate in alignment with the mask;
• forming a silicide on preslected portions of said substrate;
• and
• forming a planarization layer after formation of said silicide.