Method for increasing DRAM capacitance via use of a roughened surface bottom capacitor plate

A method for fabricating a stacked capacitor structure, for a DRAM device, on a semiconductor substrate, wherein the surface area of the stacked capacitor structure, is increased by creating crevices in the top surface of a polysilicon storage node electrode, via selective dry etching removal, of a twice annealed, titanium silicide layer, from the top surface of said polysilicon storage node electrode, comprising the steps of:

• providing a transfer gate transistor, comprised of a polysilicon gate structure, on an underlying gate insulator layer, and with source and drain regions in said semiconductor substrate, in a region of said semiconductor substrate, not covered by said polysilicon gate structure;
• depositing an insulator layer on the substrate and the transfer gate transistor;
• forming a storage node opening in said insulator layer, exposing the top surface of said source and drain region;
• depositing an in situ doped polysilicon layer, completely filling said storage node opening;
• patterning of said in situ doped polysilicon layer, to form said polysilicon storage node electrode, in said storage node opening;
• depositing a titanium layer on the polysilicon storage node electrode and the insulator layer;
• performing a first anneal procedure, to selectively form a first titanium silicide layer, on said polysilicon storage node electrode, while said titanium, on the top surface of said insulator layer remains unreacted,
• removing said titanium layer from the top surface of said insulator layer;
• performing a second anneal procedure, converting said first titanium silicide layer, to a second titanium silicide layer, and consuming regions of the top surface of said polysilicon storage node electrode, during said second anneal procedure, and resulting in a roughened top surface for said polysilicon storage node electrode, underlying said second titanium silicide layer, comprised of crevices in the top surface of said polysilicon storage node electrode;
• performing a dry etching procedure, using SF.sub.6 and Cl.sub.2 as etchants, to selectively remove said second titanium silicide layer from said roughened top surface of said polysilicon storage node electrode;
• forming a capacitor dielectric layer on said roughened top surface of said polysilicon storage node electrode;
• depositing a polysilicon layer on the capacitor dielectric layer;
• and
• patterning of said polysilicon layer to form a capacitor plate for said stacked capacitor structure.