A method for fabricating a high performance CMOS logic region, and a low cost DRAM memory region, on the same semiconductor chip, using an integrated fabrication process, comprising the steps of:
- providing a semiconductor substrate;
- providing a CMOS logic region in a first region of said semiconductor substrate;
- providing a DRAM memory region in a second region of said semiconductor substrate;
- forming a P well region, in said semiconductor substrate, in said DRAM memory region;
- forming a P well region in said semiconductor substrate, in an area of said CMOS logic region to be used for N channel MOSFET, (metal oxide semiconductor field effect transistor), devices;
- forming an N well region in said semiconductor substrate, in area of said CMOS logic region to be used for P channel MOSFET devices;
- forming a buried N type region, in said semiconductor substrate, in said DRAM memory region, isolating said DRAM region from said semiconductor substrate;
- growing a thin silicon dioxide layer on said semiconductor substrate;
- removing said thin silicon dioxide layer from said semiconductor substrate, in said CMOS logic region;
- forming a CMOS logic, silicon dioxide gate insulator layer, in said CMOS logic region, from thermal oxidation of exposed, said semiconductor substrate;
- forming a DRAM memory, silicon dioxide gate insulator layer, in said DRAM memory region, comprised of said thin silicon oxide layer, and comprised from silicon dioxide growth during thermal oxidation of said semiconductor substrate;
- depositing an undoped polysilicon layer;
- forming a composite insulator layer of silicon nitride--silicon oxide, on said undoped polysilicon layer;
- forming shallow trenches in said composite insulator layer, in said undoped polysilicon layer, in silicon dioxide gate insulator layers, and in said semiconductor substrate;
- forming shallow trench isolation regions, by filling said shallow trenches with a first silicon oxide layer;
- removal of said composite insulator;
- depositing a first silicon nitride layer on said undoped polysilicon layer;
- patterning of said first silicon nitride layer, to form a masking silicon nitride shape, on a region of said undoped polysilicon layer, overlying said N well region;
- performing an N type, POCl.sub.3 doping procedure, to a region of said undoped polysilicon layer, not covered by said masking silicon nitride shape, to create an N type polysilicon layer;
- growing a silicon dioxide layer on said N type polysilicon layer;
- removal of said masking silicon nitride shape, exposing region of said undoped polysilicon layer;
- converting the region of said undoped polysilicon layer, to a P type polysilicon layer, via a boron ion implantation procedure;
- removal of said silicon oxide layer from the top surface of said N type polysilicon layer;
- depositing a titanium nitride layer;
- depositing a titanium disilicide layer;
- depositing a second silicon nitride layer;
- forming polycide gate structures, in said DRAM memory region, comprised of said second silicon nitride layer, said titanium disilicide layer, said titanium nitride layer, and said N type polysilicon layer, on said DRAM memory, silicon dioxide gate insulator layer;
- forming a polycide gate structure, in the CMOS logic region to be used for N channel MOSFET devices, comprised of said second silicon nitride layer, said titanium disilicide layer, said titanium nitride layer, and said N type polysilicon layer, on said CMOS logic, silicon dioxide gate insulator layer;
- forming a polycide gate structure, in the CMOS logic region to be used for P type MOSFET devices, comprised of said second silicon nitride layer, said titanium disilicide layer, said titanium nitride layer, and said P type polysilicon layer, on said CMOS logic, silicon dioxide gate insulator layer;
- depositing a third silicon nitride layer;
- anisotropic dry etching, of said third silicon nitride layer, to form silicon nitride spacers, on the sides of the polycide gate structures, in said CMOS logic region;
- forming an N type, lightly doped source and drain region, in said P well region, of said CMOS logic region, under said silicon nitride spacers, using a large angle ion implantation procedure;
- forming an N type, heavily doped source and drain region, in said P well region of said CMOS logic region, in an area of said P well region, not covered by said polycide gate structure, or by said silicon nitride spacers;
- forming a P type, lightly doped source and drain region, in said N well region of said CMOS logic region, under said silicon nitride spacers, using a large angle ion implantation procedure;
- forming a P type, heavily doped source and drain region, in said N well region of said CMOS logic region, in an area of said N well region, not covered by said polycide gate structure, or by said silicon nitride spacers;
- forming titanium disilicide layers on said N type, heavily doped source and drain region, and on said P type, heavily doped source and drain regions, in said CMOS logic region;
- depositing a second silicon oxide layer;
- planarizing said second silicon oxide layer;
- removing said second silicon oxide layer from said DRAM memory region, resulting in said silicon oxide plugs, in regions between said polycide gate structures, in said CMOS logic region;
- anisotropic dry etching of said third silicon nitride layer, to form silicon nitride spacers on the sides of said polycide structures, in said DRAM memory region;
- forming an N type, lightly doped source and drain region, in said P well region of said DRAM memory region, under said silicon nitride spacers, using a large angle ion implantation procedure;
- depositing a doped polysilicon layer;
- using a CMP procedure to form doped polysilicon plugs, in said DRAM memory region, in an area between said polysilicon gate structures;
- depositing a third silicon oxide layer;
- forming storage node openings in said third silicon oxide layer, exposing the top surface of said doped polysilicon plugs, in said DRAM memory region;
- depositing a polysilicon storage node layer;
- depositing a capacitor dielectric layer;
- using a CMP procedures to remove regions of said capacitor dielectric layer, and of said polysilicon storage node layer, from the top surface of said second silicon oxide layer;
- depositing a polysilicon top plate layer;
- patterning of said polysilicon top plate layer, to form a stacked capacitor structure comprised of said polysilicon top plate layer, said capacitor dielectric layer, and of said polysilicon storage node layer, in said storage node openings, in said DRAM memory region;
- depositing a fourth silicon oxide layer;
- opening a contact hole in said fourth silicon oxide layer, to said stacked capacitor structure;
- opening via holes in said fourth silicon oxide layer, in said third silicon oxide layer, and in said second silicon oxide layer, to said N type, heavily doped source and drain region, and to said P type, heavily source and drain region, in said CMOS logic region;
- and
- forming metal structures, in said contact hole, and in said via holes, contacting said stacked capacitor structure, and contacting said N type, heavily doped source and drain region, and to said P type, heavily doped source and drain region.