Method of making dual isolation regions for logic and embedded memory devices

A method for forming a thick FOX isolation region, in an area of a semiconductor substrate to be used for a MOSFET memory region, while forming an insulator filled, trench isolation region, in an area of said semiconductor substrate to be used for a MOSFET logic region, comprising the steps of:

• forming a pad oxide layer on said semiconductor substrate;
• depositing a silicon nitride layer on said pad oxide layer;
• forming an opening in said silicon nitride layer, and in said pad oxide layer, exposing said semiconductor substrate, only in an area of said semiconductor substrate used for said MOSFET memory region;
• thermally growing a thick FOX isolation region in said semiconductor substrate, exposed in said opening in said silicon nitride layer and in said pad oxide layer;
• forming a trench opening having exposed surfaces in said silicon nitride layer, in said pad oxide layer, and in said semiconductor substrate, only in an area of said semiconductor substrate used for said MOSFET logic region;
• growing a thin silicon oxide layer on the exposed surfaces of said trench opening;
• depositing an insulator layer on the top surface of said silicon nitride layer, on the top surface of said thick FOX isolation regions, and completely filling said trench opening;
• removing said insulator layer from said top surface of said silicon nitride layer, and from said top surface of said thick FOX isolation region, and leaving said insulator layer in said trench opening, forming said insulator filled, trench isolation region, in an area of said semiconductor substrate, used for said MOSFET logic region;
• removing said silicon nitride layer, and said pad oxide layer;
• and
• forming polysilicon gate structures, and source and drain regions, in said MOSFET memory region, and in said MOSFET logic region.