Methods for reducing anomalous narrow channel effect in trench-bounded buried-channel p-MOSFETS

A method of forming a buried-channel p-MOSFET in a semiconductor substrate in which shallow trench isolation regions have been formed bordering at least edges of the buried channel which are parallel to the direction of carrier flow, said method effective for reducing anomalous narrow channel effect comprising:

• a) implanting phosphorous ions into the semiconductor substrate to form a deep phosphorous n-well adjacent to said shallow trench isolation regions, said deep phosphorous n-well being sufficiently implanted for latch-up suppression,
• b) performing one of two steps i) and ii) and
• c) performing the other of the two steps i) and ii), said two steps i) and ii) comprising
• i) implanting boron ions into the n-well to form a boron buried channel and
• ii) annealing said substrate at a low temperature to reduce damage caused by said phosphorous implantation, said low temperature being between about 750.degree. C. and about 800.degree. C., said damage causing a subsequent pile-up of the boron ions near the edges of said trench isolation, said annealing being configured to reduce said subsequent pile-up of said boron ions near the edges of said trench isolation;
• and
• d) forming a gate oxide layer on the boron buried channel by initiating a dry gate oxidation.