Method of making thin film transistors

A method of forming a thin film field effect transistor comprising the following steps:

• providing a transistor gate;
• providing a thin film transistor layer comprising first and second conductively doped active areas separated by an intervening thin film channel region, the thin film channel region being gated by the transistor gate through a gate insulator, the thin film transistor layer having a thickness;
• providing a layer of conductively doped material adjacent the thin film transistor layer;
• patterning and etching the conductively doped material to define first and second source/drain blocks;
• the first and second source/drain blocks electrically interconnecting with the respective thin film first and second active areas to define composite first and second conductively doped transistor active regions having a thickness which is greater than the thin film layer thickness;
• and
• wherein the transistor gate is provided as a bottom gate, and the steps of providing, patterning and etching to define the first and second source/drain blocks comprises:
• at least local planarizing in the vicinity of the bottom gate to provide a substantially planar upper bottom gate surface which is substantially co-planar with adjacent upper surfaces;
• after local planarizing, providing the thin film transistor layer;
• after providing the thin film transistor layer, providing and patterning a masking layer to cover the thin film channel region and upwardly expose the first and second active areas;
• after providing the masking layer, providing a layer of polysilicon over the masking layer and first and second active areas;
• and
• chemical-mechanical polishing the layer of polysilicon to at least in part define discrete first and second source/drain blocks.

A method of forming a bottom gated thin film field effect transistor comprising the following steps:

• providing a bottom gate within a layer of insulating material;
• providing first and second electrically conductive source/drain blocks elevationally higher and opposingly adjacent the bottom gate;
• providing a gate insulating layer over the bottom gate;
• and
• providing a thin film transistor layer over the first and second source/drain blocks and gate insulating layer, the thin film transistor layer electrically interconnecting with the first and second conductive source/drain blocks to define a thin film field effect transistor having opposing source/drain regions with a thickness which is greater than an intervening thin film transistor channel region.