Semiconductor package and method for fabricating the same
AssigneesAnam Semiconductor Inc., Amkor Technology, Inc.
InventorsYoung Wook Heo, Byung Joon Han
Life of this patent
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Abstract
A process for manufacturing chip size semiconductor package with a light, thin, and compact structure having a reduced size of its semiconductor chip while having an increased number of pins For the package, it is possible to use either the semiconductor chip having bond pads arranged on end portions of the chip or the semiconductor chip having bond pads arranged on the central portion of the chip. In either case, input/output terminals of the package are arranged in the form of an area array. Accordingly, when the package is mounted on an electronic appliance, its mounting area can be minimized, thereby achieving a compactness of the final product.
Claims13
A method for fabricating a semiconductor package comprising the steps of:
- providing a wafer forming semiconductor chips each having an integrated electronic circuit and a plurality of bond pads each adapted to send a signal from the electronic circuit to the outside of the package;
- forming a multi-layer film which has the same size as the wafer, consists of two non-conductive film layers and a conductive layer, and is formed by forming a conductive layer over a first non-conductive film which is a lower one of the two layers, patterning the conductive layer to form the circuit patterns, and laminating a second non-conductive film on the circuit patterns;
- attaching the multi-layer film to the wafer by adhesive means in such a manner the bond pad regions defined at the semiconductor chips of the wafer are exposed through the opened portions of the multi-layer film;
- bonding bond fingers provided at the circuit patterns of the multi-layer film to the bond pads of the semiconductor chips by wires, respectively;
- covering a sealant layer over the opened portions of the multi-layer film, thereby protecting the wires from external oxidation and erosion;
- baking the sealant layer in an oven or furnace at a temperature of 150.degree. C. or more;
- seating solder balls on solder ball lands provided at the multi-layer film, respectively, and reflowing the solder balls in the oven or furnace at a temperature of 200.degree. C. or more, thereby bonding the solder balls to the circuit patterns;
- cutting the wafer along its street lines using a sawing device so that it can be divided into individual semiconductor chips, thereby forming chip size packages having the same size as their semiconductor chips.
Dependencies are inferred from the claim text.