Method for fabricating interline-transfer CCD image sensor

A method for fabricating a solid-state image sensor comprising the steps of:

• forming selectively, in a surface side of a first-conductivity type semiconductor substrate, a first well constituted by two layers, one layer being formed from a first second-conductivity type region utilizing first ion-implantation and the other layer being formed from a second second-conductivity type region utilizing second ion-implantation, said second second-conductivity type region having an impurity concentration higher than that of said first second-conductivity type region;
• forming a photodiode region by selectively forming, in said second second-conductivity type region, a first first-conductivity type region having a depth deeper than said second second-conductivity type region, and a second-conductivity type surface layer in said first first-conductivity type region;
• forming a buried channel layer of a vertical CCD register which has a depth shallower than that of said first first-conductivity type region by selectively forming in said second second-conductivity type region a second second-conductivity type well which has a depth deeper than an impurity concentration higher than that of said second second-conductivity type region, and forming, in a surface portion of said second second-conductivity type well, a second first-conductivity type region;
• and
• forming an element isolation region by forming a second-conductivity type region on a surface portion of said second second-conductivity type region, with exception of said photodiode, said buried channel layer and a portion of said second second-conductivity type region interposed therebetween, utilizing third ion-implantation.

A method for fabricating a solid-state image sensor comprising the steps of:

• forming as a first well of a second-conductivity type region selectively in a surface of a first-conductivity type semiconductor substrate using first ion-implantation;
• forming a photodiode region by selectively forming, in said second-conductivity type region, a first first-conductivity type region and a second-conductivity type surface layer formed on said first first-conductivity type region;
• forming a second second-conductivity type well and a buried channel layer of a vertical CCD register, said second second-conductivity type well being selectively formed in said second-conductivity type region and having an impurity concentration higher than that of said second-conductivity type region, and said buried channel layer being formed in a surface portion of said second second-conductivity type well and having a depth shallower than that of said first first-conductivity type region;
• and
• forming an element isolation region by forming a high impurity concentration second-conductivity type region in a surface portion of said second second-conductivity type well, with exception of said photodiode region, said buried channel layer and a portion of said second second-conductivity type region interposed therebetween, using third ion-implantation.