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US 5,857,214 AGranted
Microprocessor with a fixed cache size selected from a predesigned set of sizes
AssigneeAdvanced Micro Devices, Inc.
InventorShankar Dey
Life of this patent
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Abstract
A microprocessor chip having a selectable size cache. The selection is accomplished by cache size logic fabricated on the chip. The cache size logic includes a cache size logic register with output select lines that are set by the designer. The select lines control the output of multiplexors that communicate either a "0" or the contents of selected bits of a virtual address register which receives the virtual address from the CPU to either a tag field register or an address field register.
Claims4
A microprocessor chip having a CPU, comprising:
- a fixed size cache wherein the size is selected from a predesigned set of sizes:
- and cache size logic having an output to coincide with the fixed size cache selected from the predesigned set of sizes;
- said cache size logic comprises:
- a virtual address register receiving a virtual address from the CPU via an address bus;
- a second register having a variable size tag field with at least one least significant bit and a variable size address field having at least one most significant bit;
- and
- a cache size select register controlling at least one connector between a selected bit in the virtual address register and the at least one least significant bit in the tag field register and at least one most significant bit in the address field register.
4 more elements
Dependencies are inferred from the claim text.