Apparatus and method for multiplexing integrated device electronics circuitry with an industry standard architecture bus

A computer system comprising:

• a central processing unit (CPU);
• a peripheral component interface (PCI) bus for interfacing with peripheral components;
• a main memory;
• a memory control to interface among the CPU, the main memory and the PCI bus;
• at least one mass memory device;
• integrated device electronics (IDE) circuitry coupled to the mass memory device;
• an industry standard architecture (ISA) bus having an expanded memory, the ISA bus for running refresh cycles to the expanded memory;
• an ISA/PCI bridge to interface the ISA bus with the PCI bus;
• multiplexing means for isolating the IDE circuitry from the ISA bus so ISA refresh cycles can run concurrently with data transfers through the IDE circuitry, wherein the multiplexing means include:
• a transceiver to selectively isolate the IDE circuitry from the ISA bus and to logically multiplex the ISA bus and the IDE circuitry such that the ISA bus may refresh the main memory while data transfers occur through the IDE circuitry;
• and
• a transceiver control to control the transceiver from the ISA/PCI bridge and to multiplex program data cycles from the IDE circuitry with the non-refresh operations from the ISA bus;
• and
• control means for controlling the multiplexing means in response to the ISA/PCI bridge.