US 5,857,116 AGranted

Circuit for disabling an address masking control signal when a microprocessor is in a system management mode

AssigneeCompaq Computer Corporation

InventorsBasem Abu Ayash, Gary W. Thome

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Abstract

A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

Claims15

Dependent claims

A computer system having corrected system management mode addressing, comprising:

a host bus;
a microprocessor coupled to said host bus and capable of operating in a system management mode and providing a system management mode indication thereof, said microprocessor including:
a set of n address outputs for collectively providing an address to said host bus;
an address mask input for receiving a masking signal;
an address mask responsive to said masking signal and operable to mask at least one of the address outputs before said address is provided to said host bus;
an input/output system controller coupled to said host bus;
one or more mass storage devices coupled to said input/output system controller and addressable by said microprocessor;
a masking control signal generator operable to selectively provide the masking signal;
an address correction circuit responsive to the system management mode indication for passing the masking signal from said masking control signal generator to said microprocessor based on the system management mode indication, said address correction circuit being operable to disable passage of the masking signal if the system management mode indication is provided and being operable to enable passage of the masking signal if the system management mode indication is not provided.

6 more elements

Dependencies are inferred from the claim text.