DMA system for re-arbitrating memory access priority during DMA transmission when an additional request is received

A DMA transmission system, comprising:

• a microprocessor generating the DMA transmission instruction and performing another task during the DMA transmission;
• DMA controlling means controlling the stream of data and addresses by performing said instruction received from said microprocessor and generating control signals for address and data buffers;
• a source memory storing data to be transmitted;
• a destination memory storing transmitted data;
• a DMA data buffer temporarily storing data of said source memory before transfer to said destination memory during the DMA transmission;
• a destination data buffer temporarily storing data transmitted between said microprocessor and said destination memory;
• a destination address buffer temporarily storing an address of said destination memory transmitted by said microprocessor;
• a source address buffer temporarily storing data transmitted between said microprocessor and said source memory;
• a multiplexer receiving a source memory address output from said DMA controlling means and a source address output from said microprocessor, and outputting one of said source memory address and said source address according to a control signal from said DMA controlling means;
• a DMA arbitrator arbitrating a memory access priority during a DMA transmission cycle when the memory access request is received from a master intending to use one of said source and destination memories during the DMA transmission;
• and
• DMA engine controlling means for requesting the memory access priority from said DMA arbitrator, and upon reception of a signal from said DMA arbitrator transmitting information regarding said DMA transmission frequency to a DMA count register.