Method and apparatus for addressing extended registers on a processor in a computer system

A method of modifying an instruction set of a target processor, said method comprising the steps of:

• providing a target processor having a first set of registers and a second set of registers;
• providing a first set of instructions for said target processor, wherein said first set of instructions are only able to address said first set of registers;
• executing instructions in at least one computer program on said target processor;
• recording an execution frequency for each instruction in said first set of instructions executed in said step of executing;
• determining an execution frequency threshold based upon said execution frequencies recorded in said recording step;
• and
• grouping instructions from said first set of instructions with an execution frequency equal to or exceeding said execution frequency threshold into said subset set of frequently executed instructions, said subset of frequently executed instructions capable of addressing registers in said second set of registers,
• whereby frequently executed instructions are able to address a register in said second set of registers located on said target processor.

A method of compiling the source code of a target computer program into a target executable program which optimizes the use of registers on a target processor, said method further comprising the steps of:

• providing a target processor having a first set of registers and a second set of registers;
• providing a first set of instructions for said target processor, wherein said first set of instructions are only able to address said first set of registers;
• providing a second set of instructions for said target processor, wherein said second set of instructions comprises a subset of frequently executed instructions within said first set of instructions wherein said second set of instructions are able to address said first set of registers and said second set of registers;
• generating a plurality of intermediate instructions from said source code of said target computer program;
• assigning at least one virtual registers to at least one intermediate instruction within said plurality of intermediate instructions, wherein a virtual register may be shared by a plurality of intermediate instructions;
• marking a virtual register as poisoned if said virtual register is assigned to at least one intermediate instruction which represents an instruction in said first set of instructions;
• allocating physical registers to each instruction assigned in said assigning step by performing the following steps:
• if a virtual register is marked as poisoned then allocating a register in said first set of registers to said instruction;
• and
• if a virtual register is not marked as poisoned then allocating a register in said second set of register to said instruction.

An apparatus for creating a target executable program from the source code of a target computer program for execution on a target processor comprising:

• a first program mechanism which provides a target processor having a first set of registers and a second set of registers;
• a second program mechanism which provides a first set of instructions for said target processor, wherein said first set of instructions are only able to address said first set of registers;
• a third program mechanism which provides a second set of instructions for said target processor, wherein said second set of instructions comprises a subset of frequently executed instructions within said first set of instructions further wherein said second set of instructions are able to address said first set of registers and said second set of registers;
• and
• a fourth program mechanism which compiles said source code into a plurality of target executable instructions wherein the registers within said second set of registers are only allocated to those target executable instructions in said second set of instructions,
• whereby frequently executed instructions are able to address a register in said second set of registers located on said target processor.

A computer program product comprising:

• a computer usable medium having computer readable program code tangibly embedded in said computer program product, the program code configured to cause the computer to create a target executable program from the source code of a target computer program for execution on a target processor, said code comprising:
• code that provides a target processor having a first set of registers and a second set of registers;
• code that provides a first set of instructions for said target processor, wherein said first set of instructions are only able to address said first set of registers;
• code that provides a second set of instructions for said target processor, wherein said second set of instructions comprises a subset of frequently executed instructions within said first set of instructions wherein said second set of instructions are able to address said first set of registers and said second set of registers;
• and
• code that compiles said source code into a plurality of target executable instructions wherein the registers within said second set of registers are only allocated to those target executable instructions in said second set of instructions,
• whereby frequently executed instructions are able to address a register in said second set of registers located on said target processor.