Branch instruction prediction apparatus
AssigneeSamsung Electronics Co., Ltd.
InventorsAdam R. Talcott, Ramesh K. Panwar
Life of this patent
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Abstract
The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of bits from a branch history register is used to first address a branch history table to obtain a plurality of candidate predictions. In a late addressing process, a second subset of bits from the branch history register is used to again address the branch history table to select one of the plurality of candidate predictions, the second subset of bits including additional branch history information loaded into the branch history register subsequent to the early addressing mode. In this way, more recent branch history information is used to predict the outcome of the given branch instruction.
Claims15
A branch prediction apparatus for predicting an outcome of a given branch instruction, comprising:
- a branch history register which stores outcomes of plural branch instructions;
- a branch history table which stores branch predictions;
- a first decoder which receives a first subset of bits from said branch history register to first address said branch history table to obtain a plurality of candidate predictions;
- and,
- a second decoder which receives a second subset of bits from said branch history register to select one of the plurality of candidate predictions, wherein the second subset of bits includes additional branch instruction outcomes loaded into said branch history register subsequent to said first decoder receiving the first subset of bits.
Dependencies are inferred from the claim text.