Cross-compiled simulation timing backannotation

A simulator adapted for simulating execution of a first executable program by a microprocesser-based device having a target microprocessor, said simulator comprising:

• a simulation microprocessor, said simulation microprocessor having operational characteristics which are different than operational characteristics of said target microprocessor;
• and
• a second executable program, said second program being-derived from a same source code program as said first program, said second program being executable by said simulation microprocessor, said second program having timing information embedded therein, said timing information pertaining to time required for said target microprocessor to execute individual portions of said first program;
• and
• wherein said timing information is embedded so as to be associated with non-branching execution blocks of said second program, and wherein said individual portions of said first program are non-branching execution blocks which correspond to said non-branching execution blocks of said second program.

A simulator adapted for simulating execution of a first executable program by a microprocessor-based device having a target microprocessor, said simulator comprising:

• a simulation microprocessor, said simulation microprocessor having operational characteristics which are different than operational characteristics of said target microprocessor;
• and
• a second executable program, said second program being derived from a same source code program as said first program, said second program being executable by said simulation microprocessor, said second program having timing information embedded therein, said timing information pertaining to time required for said target microprocessor to execute individual portions of said first program;
• and
• wherein said timing information is embedded in said second program indirectly by way of said same source code program, wherein said timing information is embedded in said same source code program in the form of a macro, and wherein operands of individual macro statements contain said timing information.

A method comprising:

• compiling a source code program so as to produce a first executable program for a first microprocessor;
• extracting timing information from said first program;
• compiling said source code program so as to produce a second executable program for a second microprocessor;
• annotating said second program with said timing information, said annotating step further including annotating said source code program with said timing information such that said timing information is annotated into said second program indirectly by way of said source code program, and said step of annotating said source code program further including inserting a macro into said source code program prior to said compiling step, said macro taking said timing information as an operand, and
• executing said second program with said second microprocessor and generating an output based on said timing information so as to inform a simulation of a microprocessor-based system, said generating step being performed by said second microprocessor when said second microprocessor is executing executable instructions corresponding to said macro.

A method comprising:

• compiling a source code program so as to produce a first executable program for a first microprocessor;
• extracting timing information from said first program;
• compiling said source code program so as to produce a second executable program for a second microprocessor;
• annotating said second program with said timing information;
• executing said second program with said second microprocessor and generating an output based on said timing information so as to perform a simulation of a microprocessor-based system, said executing step including
• ascertaining that a synchronization point has been reached based on said timing information annotated in said second program,
• informing a simulation kernel that said synchronization point has been reached,
• temporarily interrupting said executing step while a simulation of another system is performed, and then continuing said executing step after said simulation of said another system has reached said synchronization point, and
• repeating said ascertaining, informing, and temporarily interrupting steps such that the simulation of said second microprocessor and said simulation of said another system are synchronized based on said timing information annotated in said second program.

A method comprising:

• compiling a source code program so as to produce a first executable program for a first microprocessor;
• extracting timing information from said first program;
• compiling said source code program so as to produce a second executable program for a second microprocessor;
• annotating said second program with said timing information;
• wherein said timing information extracting step further comprises
• partitioning said first program into non-branching execution blocks formed of non-branching segments,
• generating first and second timing numbers for first and second instructions of one of said non-branching execution blocks, said first timing number representing an amount of time required to execute said first instruction and said second timing number representing an amount of time required to execute said second instruction,
• adding said first and second timing numbers so as to form a composite timing number, said timing information annotated into said first simulation program being based on said composite timing number, and
• repeating said generating and adding steps for substantially the entire portion of said first program to be simulated.

A method of simulating a system having first and second microprocessor-based subsystems, said first microprocessor-based subsystem having a first target microprocessor and said second microprocessor-based subsystem having a second target microprocessor, the method comprising:

• A. generating a first target program compiled for said first target microprocessor;
• B. generating a first simulation program for a simulation microprocessor used to simulate said first and second target microprocessors, said first simulation program having timing information embedded therein, said timing information pertaining to time required for said first target microprocessor to execute individual portions of said first target program;
• C. generating a second target program compiled for said second target microprocessor;
• D. generating a second simulation program for said simulation microprocessor, said second simulation program having timing information embedded therein, said timing information pertaining to time required for said second target microprocessor to execute individual portions of said second target program;
• E. defining a plurality of synchronization points which occur at predetemined virtual time intervals;
• F. executing said first simulation program with said simulation microprocessor;
• G. interrupting said executing step (F) when one of said plurality of synchronization points is reached, said interrupting step (G) occur based on said timing information embedded in said first simulation program;
• H. executing said second simulation program with said simulation microprocessor;
• I. interrupting said executing step (H) when said one of said plurality of synchronization points is reached, said interrupting step (I) occurring based on said timing information embedded in said second simulation program;
• and
• J. repeating steps (F), (G), (H) and (I) such that said first and second simulation programs are executed in a same virtual time domain as defined by said timing information embedded in said first and second simulation programs.

A simulation system comprising:

• a simulation microprocessor used to simulate a target microprocessor, said simulation microprocessor and said target microprocessor being of different types;
• a source code program;
• a compiler adapted for compiling said source code program, said compiler generating debugging information which relates lines of executable code to lines of source code;
• a first executable program derived from said source code program, said first program being generated by said compiler, said first program being formed of a first plurality of non-branching segments, and said first program being compiled for said target microprocessor;
• a second executable program derived from said source code program, said second program being formed of a second plurality of non-branching segments corresponding to said first plurality of non-branching segments, said second program being executable by said simulation microprocessor;
• a timing extractor, said timing extractor being adapted for identifying said first plurality of non-branching segments in said first program and for generating a plurality of timing numbers, said plurality of timing numbers representing an amount of time required by said target microprocessor to execute each of said first plurality of non-branching segments;
• and
• a timing inserter, said timing inserter being adapted for annotating said source code program with said plurality of timing numbers generated by said timing extractor, said source code program being annotated with a macro wherein individual macro statements take one of said timing numbers as an operand, and wherein said timing inserter utilizes said debugging information to annotate said source code program.

A method of simulating execution of a first executable program by a target microprocessor using a second executable program executed by a simulation microprocessor, the method comprising:

• compiling a source code program so as to produce said first program for said target microprocessor;
• extracting timing information from said first program, said timing information pertaining to time required for said target microprocessor to execute individual portions of said first program;
• compiling said source code program so as to produce said second program for said simulation microprocessor;
• annotating said second program with said timing information, said annotating step including providing said second program with a plurality of executable instructions that each (1) correspond to a different respective one of said individual portions of said first program and (2) take as an operand said timing information pertaining to said time required for said target microprocessor to execute said respective one of said individual portions of said first program;
• and
• executing said second program with said simulation microprocessor to simulate said execution of said first program by said target microprocessor, including generating an output based on said timing information.